公开(公告)号：US5422509A

公开(公告)日：1995-06-06

申请号：US40216

申请日：1993-04-01

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/331 ,  H01L27/06 ,  H01L29/735 ,  H01L29/50 ,  H01L29/70 ,  H01L29/78

CPC classification number: H01L29/6625 ,  H01L27/0623 ,  H01L29/735 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/126

Abstract: A bipolar control transistor, forming part of an integrated current-limiter device comprises inside an epitaxial layer superimposed over a semiconductor substrate of a first type of conductivity, a base region of a second type of conductivity accessible from a base contact and regions of collector and emitter of the first type of conductivity contained in the base region and accessible from respective collector and emitter contacts. The base region comprises at least one highly-doped deep-body region which contains almost completely said emitter region, a lightly-doped body region which contains the collector region and an intermediate-doped region which co-operates with the first deep-body region to completely contain the emitter region and a surface area of the base region that is included between the regions of collector and emitter. There is also at least one first portion of a layer of polysilicon superimposed and self-aligned with the surface area between the regions of collector and emitter and electrically connected to the collector contact of the bipolar transistor.

Abstract translation: 形成集成电流限制器件的一部分的双极性控制晶体管包括叠加在第一导电类型的半导体衬底上的外延层的内部，可从基极接触的第二类导电性的基极区域和集电极和 第一类电导率的发射极包含在基极区域中并且可从相应的集电极和发射极触点接近。 基极区域包括至少一个高度掺杂的深体区域，其包含几乎完全是所述发射极区域，包含集电极区域的轻掺杂体区域和与第一深体区域配合的中间掺杂区域 以完全包含发射极区域和包括在集电极和发射极的区域之间的基极区域的表面积。 还存在与集电极和发射极的区域之间的表面积叠置并自对准并与双极晶体管的集电极触点电连接的多晶硅层的至少一个第一部分。

公开(公告)号：US5119161A

公开(公告)日：1992-06-02

申请号：US537940

申请日：1990-06-14

Applicant: Raffaele Zambrano ,  Salvatore Musumeci ,  Salvatore Raciti

Inventor： Raffaele Zambrano ,  Salvatore Musumeci ,  Salvatore Raciti

IPC: H01L21/8222 ,  H01L21/8248 ,  H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/8248

Abstract: The problems normally linked to the creation of a power stage using BJT transistors are overcome realizing the power stage with BMFET transistors.

公开(公告)号：US07050322B2

公开(公告)日：2006-05-23

申请号：US10360840

申请日：2003-02-07

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: G11C11/22

CPC classification number: G11C11/005

Abstract: An integrated device including a first memory array having first memory cells of a nonvolatile type and a second memory array having second memory cells of a volatile type (DRAM). The first memory cells and the second memory cells are formed in a substrate of semiconductor material, and each includes a respective MOS transistor which is formed in an active region of the substrate and has a first conductive region and a respective capacitor which is formed on top of the active region and has a first electrode and a second electrode, which are separated by a dielectric region. Moreover, the first electrode of the capacitor is connected to the first conductive region of the MOS transistor. The first and the second memory cells have a structure that is substantially the same and are formed simultaneously.

公开(公告)号：US06878982B2

公开(公告)日：2005-04-12

申请号：US10615961

申请日：2003-07-08

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/8246 ,  H01L27/115 ,  H01L27/108

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the first conduction terminals, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises a plurality of plugs filled with a non-conductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material and coupled to the second conduction terminals or the control circuitry.

Abstract translation: 一种集成在半导体衬底中的铁电存储器件的接触结构，包括适当的控制电路和铁电存储器单元的矩阵阵列，其中每个单元包括连接到铁电电容器的MOS器件。 MOS器件具有第一和第二导电端子并被绝缘层覆盖。 铁电电容器具有形成在第一导电端子上方的绝缘层上的下板，并且电连接到第一导电端子，该下板被铁电材料层覆盖并电容耦合到上板。 有利地，接触结构包括在第一导电端子和铁电电容器之间填充有非导电材料的多个插塞，并且包括填充有导电材料并且耦合到第二导电端子或控制电路的多个插头。

公开(公告)号：US06734565B2

公开(公告)日：2004-05-11

申请号：US10126936

申请日：2002-04-18

Applicant: Raffaele Zambrano ,  Cesare Artoni ,  Chiara Corvasce

Inventor： Raffaele Zambrano ,  Cesare Artoni ,  Chiara Corvasce

IPC: H01L2352

CPC classification number: H01L27/11502 ,  H01L21/76877

Abstract: An integrated device having: a first conductive region; a second conductive region; an insulating layer arranged between the first and the second conductive region; at least one through opening extending in the insulating layer between the first and the second conductive region; and a contact structure formed in the through opening and electrically connecting the first conductive region and the second conductive region. The contact structure is formed by a conductive material layer that coats the side surface and the bottom of the through opening and surrounds an empty region which is closed at the top by the second conductive region. The conductive material layer preferably comprises a titanium layer and a titanium-nitride layer arranged on top of one another.

Abstract translation: 一种集成装置，具有：第一导电区域; 第二导电区域; 布置在第一和第二导电区域之间的绝缘层; 至少一个通孔，其延伸在所述第一和第二导电区域之间的绝缘层中; 以及形成在所述通孔中并且电连接所述第一导电区域和所述第二导电区域的接触结构。 接触结构由覆盖通孔的侧表面和底部的导电材料层形成，并且包围由第二导电区域封闭在顶部的空区域。 导电材料层优选地包括彼此顶部布置的钛层和氮化钛层。

公开(公告)号：USRE38510E1

公开(公告)日：2004-05-04

申请号：US08384250

申请日：1995-02-06

Applicant: Raffaele Zambrano ,  Salvatore Musumeci

Inventor： Raffaele Zambrano ,  Salvatore Musumeci

IPC: H01L21331

CPC classification number: H01L21/761 ,  H01L21/8222

Abstract: The device uses the horizontal insulating region and the buried layer as the power transistor base and emitter respectively. An epitaxial growth is interposed between the two diffusions needed to form the aforesaid regions and those needed to create the base and the emitter of the transistor of the integrated control circuit.

公开(公告)号：US06633060B2

公开(公告)日：2003-10-14

申请号：US09998602

申请日：2001-11-16

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L31062

CPC classification number: H01L27/11502 ,  H01L27/11507

Abstract: A contact structure for a ferroelectric memory device integrated in a semiconductor substrate and includes an appropriate control circuitry and a matrix array of ferroelectric memory cells, wherein each cell includes a MOS device connected to a ferroelectric capacitor. The MOS device has first and second conduction terminals and is covered with an insulating layer. The ferroelectric capacitor has a lower plate formed on the insulating layer above the first conduction terminals and connected electrically to the first conduction terminals, which lower plate is covered with a layer of a ferroelectric material and coupled capacitively to an upper plate. Advantageously, the contact structure comprises a plurality of plugs filled with a non-conductive material between the first conduction terminals and the ferroelectric capacitor, and comprises a plurality of plugs filled with a conductive material and coupled to the second conduction terminals or the control circuitry.

Abstract translation: 一种集成在半导体衬底中的铁电存储器件的接触结构，包括适当的控制电路和铁电存储器单元的矩阵阵列，其中每个单元包括连接到铁电电容器的MOS器件。 MOS器件具有第一和第二导电端子并被绝缘层覆盖。 铁电电容器具有形成在第一导电端子上方的绝缘层上的下板，并且电连接到第一导电端子，该下板被铁电材料层覆盖并电容耦合到上板。 有利地，接触结构包括在第一导电端子和铁电电容器之间填充有非导电材料的多个插塞，并且包括填充有导电材料并且耦合到第二导电端子或控制电路的多个插头。

公开(公告)号：US06579727B1

公开(公告)日：2003-06-17

申请号：US09710066

申请日：2000-11-09

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55

Abstract: A process for selectively sealing ferroelectric capacitive elements in non-volatile memory cells being integrated in a semiconductor substrate and comprising at least one MOS transistor, which process comprises at least the following steps: forming said at least one MOS transistor on the semiconductor substrate, and depositing an insulating layer over the whole surface of the semiconductor; and further comprises the steps of: depositing a first metal layer to form, using a photolithographic technique, a lower electrode of at least one ferroelectric capacitive element; depositing a layer of a dielectric material onto said first layer; depositing a second metal layer to form, using a photolithographic technique, an upper electrode of at least one ferroelectric capacitive element; depositing a layer of a sealing material onto said second metal layer; defining the dielectric material layer and sealing layer by a single photolithographic defining step, so as to pattern said dielectric layer and concurrently seal said at least one capacitive element.

Abstract translation: 一种用于选择性地密封非易失性存储单元中的铁电电容元件的方法，其集成在半导体衬底中并且包括至少一个MOS晶体管，该工艺至少包括以下步骤：在半导体衬底上形成所述至少一个MOS晶体管，以及 在半导体的整个表面上沉积绝缘层; 并且还包括以下步骤：沉积第一金属层以使用光刻技术形成至少一个铁电电容元件的下电极; 在所述第一层上沉积介电材料层; 沉积第二金属层以使用光刻技术形成至少一个铁电电容元件的上电极; 在所述第二金属层上沉积密封材料层; 通过单个光刻限定步骤限定介电材料层和密封层，以便图案化所述电介质层并同时密封所述至少一个电容元件。

公开(公告)号：US06218228B1

公开(公告)日：2001-04-17

申请号：US08856261

申请日：1997-05-14

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L218238

CPC classification number: H01L29/7802 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7395

Abstract: A DMOS device structure includes a lightly doped semiconductor layer of a first conductivity type, a plurality of lightly doped semiconductor regions of a second conductivity type extending from a top surface of the lightly doped semiconductor layer thereinto, source regions of the first conductivity type contained in the lightly doped semiconductor regions and defining channel regions. The lightly doped semiconductor regions are contained in respective enhancement regions of the lightly doped semiconductor layer of the same conductivity type as, but with a lower resistivity than, the lightly doped semiconductor layer.

Abstract translation: DMOS器件结构包括第一导电类型的轻掺杂半导体层，从其中的轻掺杂半导体层的顶表面延伸的第二导电类型的多个轻掺杂半导体区域，第一导电类型的源极区包含在 轻掺杂的半导体区域和限定沟道区域。 轻掺杂半导体区域包含在相同导电类型的轻掺杂半导体层的相应增强区域中，但是具有比轻掺杂半导体层更低的电阻率。

公开(公告)号：US5940711A

公开(公告)日：1999-08-17

申请号：US901709

申请日：1997-07-25

Applicant: Raffaele Zambrano

Inventor： Raffaele Zambrano

IPC: H01L21/265 ,  H01L21/331 ,  H01L29/10 ,  H01L29/732

CPC classification number: H01L29/66272 ,  H01L21/26586 ,  H01L29/1004 ,  H01L29/732

Abstract: A process for forming a structure of a high-frequency bipolar transistor on a layer of a semiconductor material with conductivity of a first type. The process includes forming a first shallow base region by implantation along a selected direction of implantation and using a dopant with a second type of conductivity. The region extends from a first surface of the semiconductor material layer and encloses, toward said first surface, an emitter region with conductivity of the first type. In accordance with the invention, the implantation step includes at least one process phase at which the direction of implantation is maintained at a predetermined angle significantly greatly than zero degrees from the direction of a normal line to said first surface. Preferably, the implantation angle is of about 45 degrees.

Abstract translation: 一种用于在具有第一类型的导电性的半导体材料的层上形成高频双极晶体管的结构的工艺。 该方法包括通过沿着选定的注入方向注入并使用具有第二类导电性的掺杂剂形成第一浅基极区域。 该区域从半导体材料层的第一表面延伸并且朝向所述第一表面封装具有第一类型的导电性的发射极区域。 根据本发明，植入步骤包括至少一个处理阶段，在该处理阶段，将注入方向保持在从法线方向到所述第一表面的零度以外的预定角度。 优选地，植入角度为约45度。