公开(公告)号：US09262732B2

公开(公告)日：2016-02-16

申请号：US13166501

申请日：2011-06-22

申请人： Bin Duan ,  Lap Chan

发明人： Bin Duan ,  Lap Chan

IPC分类号： G06Q10/06 ,  H04W64/00

CPC分类号： G06Q10/0631 ,  H04W64/006

摘要： A system and method of tracking action items in an enterprise data processing environment. The method includes receiving, by a client from a server, an action item that includes a location. The method further includes performing a check-in, by the client, at the location related to the action item. The method further includes performing a check-out, by the client, related to the action item. The method further includes changing, by the client, the status of the action item. In this manner, a database of action items and statuses may be developed for more effective business collaboration and business management.

摘要翻译： 跟踪企业数据处理环境中的动作项目的系统和方法。 该方法包括由客户端从服务器接收包括位置的动作项目。 该方法还包括由客户端在与该动作项目相关的位置处执行登记。 该方法还包括由客户端执行与该动作项目相关的退房。 该方法还包括由客户端改变动作项目的状态。 以这种方式，可以开发一个行动项目和状态的数据库，用于更有效的业务协作和业务管理。

公开(公告)号：US20140123068A1

公开(公告)日：2014-05-01

申请号：US13661687

申请日：2012-10-26

申请人： Lap Chan

发明人： Lap Chan

IPC分类号： G06F3/048

CPC分类号： G06F3/04817 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/04886 ,  H04M1/72519

摘要： Example systems and methods of managing content are described. In one implementation, a method accesses a first set of data, if second set of data, and menu data. The menu data is associated with multiple menu actions relevant to the first set of data and the second set of data. The method generates display data that allows a display device to present the first set of data, the second set of data, and the menu to a user such that the menu is positioned between the first set of data and the second set of data. The method receives a user selection of a menu action and, based on the user selection, generates a graphical object that allows the user to indicate whether to apply the selected menu action to the first set of data or the second set of data.

摘要翻译： 描述了管理内容的示例系统和方法。 在一个实现中，一种方法访问第一组数据，如果是第二组数据，则菜单数据。 菜单数据与与第一组数据和第二组数据相关的多个菜单操作相关联。 该方法产生允许显示设备向用户呈现第一组数据，第二组数据和菜单的显示数据，使得菜单位于第一组数据和第二组数据之间。 该方法接收菜单动作的用户选择，并且基于用户选择，生成允许用户指示是否将所选择的菜单动作应用于第一组数据或第二组数据的图形对象。

公开(公告)号：US07932152B2

公开(公告)日：2011-04-26

申请号：US12025789

申请日：2008-02-05

申请人： Will Wong ,  Lap Chan ,  Alan Lek

发明人： Will Wong ,  Lap Chan ,  Alan Lek

IPC分类号： H01L21/8234

CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/823462 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the primary region to expose the substrate. The structure is exposed to an oxidizing medium. This forms a second layer, for example, of an oxide material primary region of the substrate. The second layer has a second thickness. Additionally, at least a portion of said first layer is converted to a third layer, for example, of an oxynitride material. The third layer has a third thickness.

摘要翻译： 一种在基板上形成集成电路结构的方法，所述基板包括主区域和次区域。 在衬底上形成第一厚度的第一材料的第一层。 第一层的一部分在主区域上被去除以暴露衬底。 该结构暴露于氧化介质。 这形成例如基板的氧化物材料主区域的第二层。 第二层具有第二厚度。 另外，所述第一层的至少一部分被转换成例如氮氧化物材料的第三层。 第三层具有第三厚度。

公开(公告)号：US20050196931A1

公开(公告)日：2005-09-08

申请号：US11123748

申请日：2005-05-04

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L29/737

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A lateral heterojunction bipolar transistor (HBT), comprising a semiconductor substrate having having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 一种横向异质结双极晶体管（HBT），包括在半导体衬底上具有第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US20050145953A1

公开(公告)日：2005-07-07

申请号：US10752454

申请日：2004-01-05

申请人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

发明人： Lap Chan ,  Jia Zheng ,  Purakh Verma ,  Jian Li ,  Shao-fu Chu

IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L31/113

CPC分类号： H01L29/66242 ,  H01L21/8249 ,  H01L27/0623

摘要： A method of manufacturing a BiCMOS integrated circuit including a CMOS transistor having a gate structure, and a heterojunction bipolar transistor having an extrinsic base structure. A substrate is provided, and a polysilicon layer is formed over the substrate. The gate structure and the extrinsic base structure are formed in the polysilicon layer. A plurality of contacts is formed through the interlevel dielectric layer to the CMOS transistor and the heterojunction bipolar transistor.

摘要翻译： 一种制造包括具有栅极结构的CMOS晶体管的BiCMOS集成电路的方法和具有外在基极结构的异质结双极晶体管。 提供衬底，并且在衬底上形成多晶硅层。 栅极结构和非本征基极结构形成在多晶硅层中。 多个触点通过层间介质层形成到CMOS晶体管和异质结双极晶体管。

公开(公告)号：US20050101096A1

公开(公告)日：2005-05-12

申请号：US10703284

申请日：2003-11-06

申请人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

发明人： Jian Li ,  Lap Chan ,  Purakh Verma ,  Jia Zheng ,  Shao-Fu Chu

IPC分类号： H01L21/331 ,  H01L29/737 ,  H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/737

摘要： A method for manufacturing a lateral heterojunction bipolar transistor (HBT) is provided comprising a semiconductor substrate having a first insulating layer over the semiconductor substrate. A base trench is formed in a first silicon layer over the first insulating layer to form a collector layer over an exposed portion of the semiconductor substrate and an emitter layer over the first insulating layer. A semiconductive layer is formed on the sidewalls of the base trench to form a collector structure in contact with the collector layer and an emitter structure in contact with the emitter layer. A base structure is formed in the base trench. A plurality of connections is formed through an interlevel dielectric layer to the collector layer, the emitter layer, and the base structure. The base structure preferably is a compound semiconductive material of silicon and at least one of silicon-germanium, silicon-germanium-carbon, and combinations thereof.

摘要翻译： 提供一种用于制造横向异质结双极晶体管（HBT）的方法，包括半导体衬底上的第一绝缘层的半导体衬底。 基底沟槽形成在第一绝缘层上的第一硅层中，以在半导体衬底的暴露部分和第一绝缘层上的发射极层之上形成集电极层。 半导体层形成在基底沟槽的侧壁上，以形成与集电极层接触的集电极结构和与发射极层接触的发射极结构。 基底结构形成在基底沟槽中。 通过层间电介质层到集电极层，发射极层和基底结构形成多个连接。 基底结构优选是硅的化合物半导体材料和硅 - 锗，硅 - 锗 - 碳及其组合中的至少一种。

公开(公告)号：US20050009357A1

公开(公告)日：2005-01-13

申请号：US10909523

申请日：2004-08-02

申请人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

发明人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/26506

摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

公开(公告)号：US06541327B1

公开(公告)日：2003-04-01

申请号：US09760123

申请日：2001-01-16

申请人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

发明人： Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng

IPC分类号： H01L218238

CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66575

摘要： A method to form elevated source/drain (S/D) over staircase shaped openings in insulating layers. A gate structure is formed over a substrate. The gate structure is preferably comprised of a gate dielectric layer, gate electrode, first spacers, and hard mask. A first insulating layer is formed over the substrate and the gate structure. A resist layer is formed having an opening over the gate structure and over a lateral area adjacent to the gate structure. We etch the insulating layer through the opening in the resist layer. The etching removes a first thickness of the insulating layer to form a source/drain (S/D) opening. We remove the first spacers and hardmask to form a source/drain (S/D) contact opening. We implant ions into the substrate through the source/drain (S/D) contact opening to form lightly doped drain regions. We form second spacers on the sidewalls of the gate electrode and the gate dielectric and on the sidewalls of the insulating layer in the source/drain (S/D) contact opening and the source/drain (S/D) opening. A conductive layer is deposited over the gate electrode, the insulating layer. The conductive layer is planarized to exposed the insulating layer to form elevated source/drain (S/D) blocks on a staircase shape insulating layer.

摘要翻译： 一种在绝缘层中的阶梯形开口形成升高的源极/漏极（S / D）的方法。 栅极结构形成在衬底上。 栅极结构优选由栅极电介质层，栅电极，第一间隔物和硬掩模组成。 在衬底和栅极结构之上形成第一绝缘层。 形成抗蚀剂层，其具有在栅极结构上方的开口以及与栅极结构相邻的横向区域。 我们通过抗蚀剂层中的开口蚀刻绝缘层。 蚀刻去除绝缘层的第一厚度以形成源极/漏极（S / D）开口。 我们移除第一个垫片和硬掩模以形成一个源极/漏极（S / D）接触开口。 我们通过源极/漏极（S / D）接触开口将离子注入到衬底中，以形成轻掺杂的漏极区。 我们在源极/漏极（S / D）接触开口和源极/漏极（S / D）开口中的栅电极和栅极电介质的侧壁和绝缘层的侧壁上形成第二间隔物。 在栅电极，绝缘层上沉积导电层。 导电层被平坦化以暴露绝缘层，以在阶梯形绝缘层上形成升高的源极/漏极（S / D）块。

公开(公告)号：US06531750B2

公开(公告)日：2003-03-11

申请号：US09943306

申请日：2001-08-31

申请人： Lap Chan ,  Cher Liang Cha ,  Ravishankar Sundaresan

发明人： Lap Chan ,  Cher Liang Cha ,  Ravishankar Sundaresan

IPC分类号： H01L2976

CPC分类号： H01L29/6659 ,  H01L21/28044 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4916 ,  H01L29/4941 ,  H01L29/665 ,  H01L29/66545

摘要： A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions. The second electrode layer is etched through to form separate conductive connections. An intermetal dielectric layer is deposited. The intermetal dielectric layer is etched through to form contact openings. A metal layer is deposited and etched through to form separate metal interconnects. A passivation layer is deposited, and the integrated circuit is completed.

摘要翻译： 实现了形成浅结MOSFET的方法。 栅极氧化层形成在衬底上。 沉积多晶硅或金属的第一电极层。 沉积氮化硅层。 氮化硅层和第一电极层被蚀刻通过以形成临时MOSFET栅极。 将离子注入到衬底中以形成轻掺杂的结。 沉积间隔层。 间隔层和栅极氧化物层被各向异性地蚀刻以形成侧壁间隔物。 将离子注入到衬底中以形成重掺杂的结。 蚀刻掉氮化硅层。 多晶硅或金属的第二电极层沉积在衬底，侧壁间隔物和第一多晶硅层上。 将第二电极层抛光到侧壁间隔物的顶表面以完成MOSFET并形成永久栅极和与源极和漏极结的导电连接。 蚀刻第二电极层以形成分开的导电连接。 沉积金属间电介质层。 金属间电介质层被蚀刻穿过以形成接触开口。 金属层被沉积​​并蚀刻通过以形成单独的金属互连。 沉积钝化层，并且集成电路完成。

公开(公告)号：US06436770B1

公开(公告)日：2002-08-20

申请号：US09721720

申请日：2000-11-27

申请人： Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee

发明人： Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee

IPC分类号： H01L21332

CPC分类号： H01L29/7827 ,  H01L29/42356 ,  H01L29/66666

摘要： A method for a vertical MOS transistor whose vertical channel width can be accurately defined and controlled. Isolation regions are formed in a substrate. The isolation regions defining an active area. Then, we form a source region in the active area. A dielectric layer is formed over the active area and the isolation regions. We form a barrier layer over the dielectric layer. We form an opening in the barrier layer. A gate layer is formed in the opening. We form an insulating layer over the conductive layer and the barrier layer. We form a gate opening through the insulating layer, the gate layer and the dielectric layer to expose the source region. Gate dielectric spacers are formed over the sidewalls of the gate layer. Then, we form a conductive plug filling the gate opening. The insulating layer is removed. We form a drain region in top and side portions of the conductive plug and form doped gate regions in the gate layer. The remaining portions of the conductive plug comprise a channel region. A channel length is between the top of the source region and the drain region. We form an interlevel dielectric layer over the barrier layer, the gate layer, and the conductive plug. Contacts are formed through the interlevel dielectric layer to the doped gate regions, the drain region and the source region.

摘要翻译： 一种垂直MOS晶体管的方法，其垂直沟道宽度可以被精确地限定和控制。 在衬底中形成隔离区。 隔离区限定有效区域。 然后，我们在活动区域​​中形成一个源区域。 在有源区域和隔离区域上形成介电层。 我们在电介质层上形成阻挡层。 我们在屏障层形成一个开口。 在开口中形成栅极层。 我们在导电层和阻挡层上形成绝缘层。 我们通过绝缘层，栅极层和电介质层形成栅极开口以暴露源极区域。 栅极电介质隔离物形成在栅极层的侧壁上。 然后，我们形成一个填充门开口的导电塞。 绝缘层被去除。 我们在导电插塞的顶部和侧部形成漏极区，并在栅极层中形成掺杂的栅极区。 导电插塞的其余部分包括沟道区域。 沟道长度在源极区域的顶部和漏极区域之间。 我们在阻挡层，栅极层和导电插塞上形成层间电介质层。 通过层间介质层与掺杂栅极区，漏极区和源极区形成触点。