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公开(公告)号：US07548103B2
公开(公告)日：2009-06-16
申请号：US11553022
申请日：2006-10-26
IPC分类号： H03K3/00
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356156
摘要： A storage device and methods thereof are disclosed. The device includes a clock control module and a latch. During normal operation, the clock control module provides a periodic clock signal to a clock input of the latch, allowing the latch to operate normally. In a low power mode of operation, the clock control module provides a constant signal to the clock input of the latch so that the latch retains stored data during the low power mode of operation. The storage device can also include a power control module that provides a first power level to the latch in the normal mode of operation and a second power level during the second mode of operation.
摘要翻译： 公开了一种存储装置及其方法。 该装置包括时钟控制模块和锁存器。 在正常操作期间，时钟控制模块向锁存器的时钟输入提供周期性的时钟信号，允许锁存器正常工作。 在低功耗操作模式下，时钟控制模块向锁存器的时钟输入提供恒定的信号，使得锁存器在低功耗操作模式期间保持存储的数据。 存储设备还可以包括功率控制模块，其在正常操作模式下向锁存器提供第一功率电平，并且在第二操作模式期间提供第二功率电平。
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公开(公告)号：US20080100363A1
公开(公告)日：2008-05-01
申请号：US11553022
申请日：2006-10-26
IPC分类号： H03K3/00
CPC分类号： H03K3/35625 , H03K3/012 , H03K3/356156
摘要： A storage device and methods thereof are disclosed. The device includes a clock control module and a latch. During normal operation, the clock control module provides a periodic clock signal to a clock input of the latch, allowing the latch to operate normally. In a low power mode of operation, the clock control module provides a constant signal to the clock input of the latch so that the latch retains stored data during the low power mode of operation. The storage device can also include a power control module that provides a first power level to the latch in the normal mode of operation and a second power level during the second mode of operation.
摘要翻译： 公开了一种存储装置及其方法。 该装置包括时钟控制模块和锁存器。 在正常操作期间，时钟控制模块向锁存器的时钟输入提供周期性的时钟信号，允许锁存器正常工作。 在低功耗操作模式下，时钟控制模块向锁存器的时钟输入提供恒定的信号，使得锁存器在低功耗操作模式期间保持存储的数据。 存储设备还可以包括功率控制模块，其在正常操作模式下向锁存器提供第一功率电平，并且在第二操作模式期间提供第二功率电平。
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23.发明授权公开(公告)号：US08943292B2
公开(公告)日：2015-01-27
申请号：US11552817
申请日：2006-10-25
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译： 一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易 第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。 第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。 每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。
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公开(公告)号：US08489906B2
公开(公告)日：2013-07-16
申请号：US12786916
申请日：2010-05-25
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3287 , H03K19/0016 , Y02D10/171
摘要： A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.
摘要翻译： 处理器包括第一虚拟终端，第二虚拟终端，耦合到第一虚拟终端的用于向第一虚拟终端提供电流的电路，耦合在第一虚拟终端和第二虚拟终端之间的第一调节晶体管，耦合到第一虚拟终端 与第一调节晶体管并联，用于通过将第二虚拟端子直接连接到第一虚拟端子来选择性地禁用第一调节晶体管，耦合在第二虚拟端子和第一电源电压端子之间的第二调节晶体管和第二禁止晶体管 与第二调节晶体管并联，用于通过将第二虚拟端子直接连接到第一电源电压端子来选择性地禁用第二调节晶体管。
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25.发明授权Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand 有权用于确定第一操作数和第二操作数的逻辑和是否与第三操作数相同的技术公开(公告)号：US08380779B2
公开(公告)日：2013-02-19
申请号：US12474451
申请日：2009-05-29
IPC分类号： G06F7/50
CPC分类号： G06F7/02 , G06F7/48 , G06F12/0864
摘要： A system is used to determine if a sum of a first operand and a second operand is the same as a third operand wherein a comparison to the third operand is of variable length. This is particularly useful in a content addressable memory (CAM) where the likelihood of hit is commonly improved over a set associative cache and allows for the CAM to identify different things. For example, an entry can be one length to identify a page of a memory and another entry be a different length to identify a page of memory. This is better understood by reference to the following description and the drawings.
摘要翻译： 系统用于确定第一操作数和第二操作数的和是否与第三操作数相同，其中与第三操作数的比较具有可变长度。 这在内容可寻址存储器（CAM）中特别有用，其中命中的可能性在集合的关联高速缓存中通常被改善，并允许CAM识别不同的事物。 例如，条目可以是识别存储器的页面的一个长度，而另一个条目是不同的长度以标识存储器页面。 通过参考以下描述和附图可以更好地理解这一点。
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公开(公告)号：US08365036B2
公开(公告)日：2013-01-29
申请号：US12560999
申请日：2009-09-16
CPC分类号： G06F11/1012
摘要： A memory system includes a memory array. The memory array includes a plurality of storage locations arranged in rows and columns. The memory system includes error correction circuitry that generates correct data bits from data bits of the memory array and error correction bits. The data bits received by the error correction circuitry are divided in subgroups where each subgroup of data bits is used to generate a subgroup of the correct data bits. The subgroups of data bits are stored in a row of the memory array at locations that are interleaved with each other.
摘要翻译： 存储器系统包括存储器阵列。 存储器阵列包括以行和列布置的多个存储位置。 存储器系统包括纠错电路，其从存储器阵列的数据位和纠错位产生正确的数据位。 由纠错电路接收的数据位被划分成子组，其中每个子组的数据位用于产生正确数据位的子组。 数据位的子组在相互交错的位置存储在存储器阵列的一行中。
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公开(公告)号：US20110296211A1
公开(公告)日：2011-12-01
申请号：US12786916
申请日：2010-05-25
CPC分类号： G06F1/3203 , G06F1/3287 , H03K19/0016 , Y02D10/171
摘要： A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.
摘要翻译： 处理器包括第一虚拟终端，第二虚拟终端，耦合到第一虚拟终端的用于向第一虚拟终端提供电流的电路，耦合在第一虚拟终端和第二虚拟终端之间的第一调节晶体管，耦合到第一虚拟终端 与第一调节晶体管并联，用于通过将第二虚拟端子直接连接到第一虚拟端子来选择性地禁用第一调节晶体管，耦合在第二虚拟端子和第一电源电压端子之间的第二调节晶体管和第二禁止晶体管 与第二调节晶体管并联，用于通过将第二虚拟端子直接连接到第一电源电压端子来选择性地禁用第二调节晶体管。
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28.发明授权Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access 有权流水线标签和信息数组访问，与信息访问相对应的标签的推测检索公开(公告)号：US07984229B2
公开(公告)日：2011-07-19
申请号：US11684529
申请日：2007-03-09
IPC分类号： G06F12/00
CPC分类号： G06F12/0895 , Y02D10/13
摘要： A cache design is described in which corresponding accesses to tag and information arrays are phased in time, and in which tags are retrieved (typically speculatively) from a tag array without benefit of an effective address calculation subsequently used for a corresponding retrieval from an information array. In some exploitations, such a design may allow cycle times (and throughput) of a memory subsystem to more closely match demands of some processor and computation system architectures. Our techniques seek to allow early (indeed speculative) retrieval from the tag array without delays that would otherwise be associated with calculation of an effective address eventually employed for a corresponding retrieval from the information array. Speculation can be resolved using the eventually calculated effective address or using separate functionality. In some embodiments, we use calculated effective addresses for way selection based on tags retrieved from the tag array.
摘要翻译： 描述了一种高速缓存设计，其中对标签和信息数组的相应访问在时间上是相位的，并且其中从标签数组中检索（通常是推测性地）的标签，而不受随后用于从信息数组的相应检索的有效地址计算的益处 。 在一些开发中，这样的设计可以允许存储器子系统的周期时间（和吞吐量）更接近地匹配一些处理器和计算系统架构的需求。 我们的技术旨在允许从标签数组中提前（确实是推测性的）检索，而不会延迟，否则将与从信息数组中相应检索最终采用的有效地址的计算相关联。 可以使用最终计算的有效地址或使用单独的功能来解决投机。 在一些实施例中，我们使用基于从标签阵列检索的标签的方法选择的计算的有效地址。
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公开(公告)号：US20110119672A1
公开(公告)日：2011-05-19
申请号：US12618311
申请日：2009-11-13
IPC分类号： G06F9/46
CPC分类号： G06F9/5044 , Y02D10/22
摘要： A multi-core system on a chip (200) is described in which a speed information for each core (210, 220, 230, 240), such as the maximum operation speed (Fmax), is extracted and stored in a storage device, such as a device control registry (215), where it may be accessed and used by the operating system when allocating workload among the cores by selecting the fasted core (e.g, 210) to run any applications or tasks that can not be executed on a plurality of cores.
摘要翻译： 描述了一种芯片上的多核系统（200），其中提取每个核心（210,220,230,240）的速度信息（如最大运行速度（Fmax））并将其存储在存储装置中， 例如设备控制注册表（215），其中当通过选择禁止的核心（例如，210）来运行任何不能执行的应用程序或任务时，操作系统可以在操作系统之间分配工作负载时，访问和使用它们 多个核心。
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公开(公告)号：US07825720B2
公开(公告)日：2010-11-02
申请号：US12372997
申请日：2009-02-18
IPC分类号： G05F1/10
摘要： A circuit has a first transistor having a first current electrode coupled to a first supply voltage terminal and a second current electrode coupled to a virtual supply voltage node. A second transistor has a first current electrode coupled to the first supply voltage terminal and a control electrode coupled to the virtual supply voltage node. A first load has an input and has an output coupled to a second current electrode of the second transistor. A third transistor has a control electrode coupled to the output of the first load. A second load has an input coupled to the first supply voltage terminal, and has an output that is coupled to both a control electrode of the first transistor and a first current electrode of the third transistor. The virtual supply voltage node provides an operating voltage to a circuit module that alternates between normal and drowsy operating modes.
摘要翻译： 电路具有第一晶体管，其具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的第二电流电极。 第二晶体管具有耦合到第一电源电压端子的第一电流电极和耦合到虚拟电源电压节点的控制电极。 第一负载具有输入并且具有耦合到第二晶体管的第二电流电极的输出。 第三晶体管具有耦合到第一负载的输出的控制电极。 第二负载具有耦合到第一电源电压端子的输入，并且具有耦合到第一晶体管的控制电极和第三晶体管的第一电流电极两者的输出。 虚拟电源电压节点向在正常和困倦的操作模式之间交替的电路模块提供工作电压。
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