公开(公告)号：US09536978B2

公开(公告)日：2017-01-03

申请号：US14198430

申请日：2014-03-05

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Ryohei Nega ,  Masaaki Kanazawa ,  Takashi Inoue

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/15 ,  H01L29/20

CPC classification number: H01L29/66462 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/7787

Abstract: To improve performance of a semiconductor device. For example, on the assumption that a superlattice layer is inserted between a buffer layer and a channel layer, a concentration of acceptors introduced into nitride semiconductor layers forming a part of the superlattice layer is higher than a concentration of acceptors introduced into nitride semiconductor layers forming the other part of the superlattice layer. That is, the concentration of acceptors introduced into the nitride semiconductor layers having a small band gap is higher than the concentration of acceptors introduced into the nitride semiconductor layers having a large band gap.

Abstract translation: 提高半导体器件的性能。 例如，假设超晶格层被插入在缓冲层和沟道层之间，则导入形成超晶格层的一部分的氮化物半导体层中的受主的浓度高于形成氮化物半导体层的受主的浓度 超晶格层的另一部分。 也就是说，导入具有小带隙的氮化物半导体层的受主的浓度高于导入具有大带隙的氮化物半导体层的受主的浓度。

公开(公告)号：US09368609B2

公开(公告)日：2016-06-14

申请号：US14332954

申请日：2014-07-16

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Tatsuo Nakayama ,  Takashi Inoue

IPC: H01L29/205 ,  H01L29/778 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7787 ,  H01L21/28264 ,  H01L29/0692 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device has a channel layer formed above a substrate, a barrier layer formed over the channel layer and having a band gap larger than that of the channel layer, a trench passing through the barrier layer as far as a midway of the channel layer, and a gate electrode disposed byway of a gate insulation film in the inside of the trench. Then, the end of the bottom of the trench is in a rounded shape and the gate insulation film in contact with the end of the bottom of the trench is in a rounded shape. By providing the end of the bottom of the trench with a roundness as described above, a thickness of the gate insulation film situated between the end of the bottom of the gate electrode and the end of the bottom of the trench can be decreased. Thus, the channel is formed also at the end of the bottom of the trench to reduce the resistance of the channel.

Abstract translation: 半导体器件具有在衬底上形成的沟道层，形成在沟道层上方并且具有比沟道层大的带隙的势垒层的沟道层，通过阻挡层的沟道至沟道层的中间， 以及在沟槽内部通过栅极绝缘膜设置的栅电极。 然后，沟槽底部的端部为圆形，并且与沟槽底部的端部接触的栅极绝缘膜为圆形。 通过如上所述地提供具有圆度的沟槽底部的端部，可以减小位于栅电极的底部端部和沟槽底部端部之间的栅极绝缘膜的厚度。 因此，沟道也形成在沟槽底部的端部以减小沟道的电阻。

公开(公告)号：US09306027B2

公开(公告)日：2016-04-05

申请号：US14548527

申请日：2014-11-20

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Toshiyuki Takewaki ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/66 ,  H01L29/51 ,  H01L29/778 ,  H01L29/205 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/518 ,  H01L23/291 ,  H01L23/3171 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/4236 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7787 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.

Abstract translation: 改善了半导体器件的特性。 半导体器件形成为具有在衬底，阻挡层，在开口区域中穿过阻挡层的沟槽并且到达沟道层的某一点的沟槽层，布置在沟槽中的栅极电极 栅极绝缘膜，以及形成在开口区域外侧的阻挡层上的绝缘膜。 然后，绝缘膜具有富Si硅氮化膜和位于其下方的富氮氮化硅膜的叠层结构。 因此，绝缘膜的上层被设定为富Si硅氮化膜。 这使得能够提高击穿电压，并且还能够提高耐蚀刻性。 而绝缘膜的下层被设定为富N的氮化硅膜。 这可以抑制崩溃。

公开(公告)号：US09269803B2

公开(公告)日：2016-02-23

申请号：US13937846

申请日：2013-07-09

Applicant: Renesas Electronics Corporation

Inventor： Yasuhiro Okamoto ,  Takashi Inoue ,  Tatsuo Nakayama ,  Ryohei Nega ,  Masaaki Kanazawa ,  Hironobu Miyamoto

IPC: H01L29/78 ,  H01L21/8252 ,  H01L29/66 ,  H01L29/778 ,  H01L29/51 ,  H01L29/20

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.

Abstract translation: 提高了由氮化物半导体材料制成的场效应晶体管的可靠性。 欧姆电极包括被隔离以彼此分离的多个单元电极。 由此，能够防止在y轴方向（负方向）在单位电极中流通导通电流。 此外，在各单元电极中，可以防止沿y轴方向（负方向）流动的通态电流的电流密度增加。 结果，可以提高欧姆电极的电迁移电阻。

公开(公告)号：US20150041821A1

公开(公告)日：2015-02-12

申请号：US14330995

申请日：2014-07-14

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Masaaki Kanazawa ,  Yasuhiro Okamoto ,  Takashi Inoue ,  Hironobu Miyamoto ,  Ryohei Nega

IPC: H01L29/66 ,  H01L29/20 ,  H01L29/45 ,  H01L29/78

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/7786 ,  H01L29/78

Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1−x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0

Abstract translation: 电极与AlGaN层欧姆接触。 半导体器件SD具有氮化物半导体层GN2和Al x Ga（1-x）N层AGN（以下称为“AlGaN层AGN”）和Al电极DE，SE。 在AlGaN层AGN中，满足0

公开(公告)号：US20180233590A1

公开(公告)日：2018-08-16

申请号：US15923787

申请日：2018-03-16

Applicant: Renesas Electronics Corporation

Inventor： Takashi Inoue ,  Tatsuo Nakayama ,  Yuji Ando ,  Yasuhiro Murase ,  Kazuki Ota ,  Hironobu Miyamoto ,  Katsumi Yamanoguchi ,  Naotaka Kuroda ,  Akio Wakejima ,  Yasuhiro Okamoto

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/20 ,  H01L29/06 ,  H01L29/15 ,  H01L29/205

CPC classification number: H01L29/7783 ,  H01L29/0607 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/42316 ,  H01L29/7787

Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer). To gate length Lg of a FET to be prepared, a sum a of layer thicknesses of an electron supply layer and a channel layer is selected so as to fulfill Lg/a≥5, and in such a case, the layer thickness of the channel layer is selected in a range of not exceeding 5 times (about 500 Å) as long as a de Broglie wavelength of two-dimensional electron gas accumulated in the channel layer in room temperature.

公开(公告)号：US09837519B2

公开(公告)日：2017-12-05

申请号：US15345880

申请日：2016-11-08

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo Nakayama ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/66 ,  H01L29/778 ,  H01L23/522 ,  H01L29/15 ,  H01L29/417 ,  H01L29/861 ,  H01L29/20 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/10

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device includes a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

公开(公告)号：US09306051B2

公开(公告)日：2016-04-05

申请号：US14590433

申请日：2015-01-06

Applicant: Renesas Electronics Corporation

Inventor： Yoshinao Miura ,  Tatsuo Nakayama ,  Takashi Inoue ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/423 ,  H01L29/205 ,  H01L29/20 ,  H01L29/201 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7787 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7783

Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.

Abstract translation: 提供具有改进特性的半导体器件。 半导体器件在其衬底上具有第一缓冲层（GaN），第二缓冲层（AlGaN），沟道层和势垒层，穿过阻挡层并到达沟道层中间的沟槽 通过栅极绝缘膜放置在沟槽中的栅电极，以及分别形成在栅极两侧的源电极和漏电极。 通过到达第一缓冲层的通孔中的耦合部分，缓冲层和源电极彼此电耦合。 由于在这两个缓冲层之间的界面附近产生的二维电子气，所以半导体器件可以具有增加的阈值电压和改善的常关特性。

公开(公告)号：US20150221757A1

公开(公告)日：2015-08-06

申请号：US14604796

申请日：2015-01-26

Applicant: Renesas Electronics Corporation

Inventor： Tatsuo NAKAYAMA ,  Hironobu Miyamoto ,  Yasuhiro Okamoto ,  Yoshinao Miura ,  Takashi Inoue

IPC: H01L29/778 ,  H01L23/522 ,  H01L29/15

CPC classification number: H01L29/7783 ,  H01L23/5226 ,  H01L27/0605 ,  H01L29/0649 ,  H01L29/1066 ,  H01L29/1075 ,  H01L29/1087 ,  H01L29/155 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.

Abstract translation: 提高了半导体器件的特性。 半导体器件被配置为提供穿透阻挡层的沟槽，并且到达n +层，n型层，p型层，沟道层和势垒层中的沟道层的中间部分，其中 形成在基板上方，通过栅极绝缘膜布置在沟槽内的栅电极，以及形成在栅电极两侧的势垒层上方的源电极和漏电极。 n型层和漏电极通过到达n +层的连接部分彼此电耦合。 p型层和源电极通过到达p型层的连接部分彼此电耦合。 在源电极和漏电极之间设置包括p型层和n型层的二极管，从而防止由雪崩击穿引起的元件断裂。

公开(公告)号：US20150115323A1

公开(公告)日：2015-04-30

申请号：US14582624

申请日：2014-12-24

Applicant: Renesas Electronics Corporation

Inventor： Tohru Kawai ,  Takashi Inoue ,  Tatsuo Nakayama ,  Yasuhiro Okamoto ,  Hironobu Miyamoto

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/778 ,  H01L21/76895 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/41758 ,  H01L29/4236 ,  H01L29/452 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7783 ,  H01L29/7786 ,  H01L29/7789

Abstract: A semiconductor device including a first nitride semiconductor layer formed over a substrate, a second nitride semiconductor layer formed on the first nitride semiconductor layer and having a band gap wider than that of the first nitride semiconductor layer, a trench penetrating through the second nitride semiconductor layer to reach the middle of the first nitride semiconductor layer, a conductive film formed at a corner portion corresponding to an end portion of a bottom surface of the trench and a gate electrode disposed via a gate insulating film inside the trench including a region on the conductive film.

Abstract translation: 一种半导体器件，包括在衬底上形成的第一氮化物半导体层，形成在第一氮化物半导体层上并且具有比第一氮化物半导体层的带隙宽的带隙的第二氮化物半导体层，穿过第二氮化物半导体层的沟槽 为了到达第一氮化物半导体层的中间，形成在对应于沟槽的底面的端部的角部的导电膜和经沟槽内部的栅极绝缘膜设置的栅电极，包括导电 电影。