公开(公告)号：US20140136869A1

公开(公告)日：2014-05-15

申请号：US13674476

申请日：2012-11-12

申请人： Greg Sadowski ,  Alexander J. Branover ,  Maurice B. Steinman

发明人： Greg Sadowski ,  Alexander J. Branover ,  Maurice B. Steinman

IPC分类号： G06F1/32

CPC分类号： G06F1/3212 ,  G06F1/3287 ,  Y02D10/171 ,  Y02D10/174

摘要： Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.

摘要翻译： 公开了各种计算设备和管理功耗的方法。 一方面，提供一种管理具有电池的计算装置的功耗的方法。 该方法包括在连接的待机活动状态和连接的待机空闲状态之间循环计算设备。 连接的待机空闲状态的持续时间至少部分地基于电池的充电水平来设定。

公开(公告)号：US08645639B2

公开(公告)日：2014-02-04

申请号：US13600614

申请日：2012-08-31

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US08566628B2

公开(公告)日：2013-10-22

申请号：US12436439

申请日：2009-05-06

申请人： Alexander Branover ,  Maurice B. Steinman ,  Ming L. So ,  Xiao Gang Zheng

发明人： Alexander Branover ,  Maurice B. Steinman ,  Ming L. So ,  Xiao Gang Zheng

IPC分类号： G06F1/32

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3253 ,  Y02D10/151

摘要： A processor integrated circuit has one or more processor cores and a power management controller in a North-Bridge that generates a first power state recommendation for the one or more processor cores. The North-Bridge also receives a second power state recommendation from a South-Bridge integrated circuit. The North-Bridge determines a final power state for the one or more processor cores based on the first and second power state recommendations.

摘要翻译： 处理器集成电路具有一个或多个处理器核心和北桥中的功率管理控制器，其为一个或多个处理器核心生成第一功率状态推荐。 北桥还从南桥集成电路获得了第二个功率状态建议。 北桥基于第一和第二功率状态建议确定一个或多个处理器核的最终功率状态。

公开(公告)号：US08266389B2

公开(公告)日：2012-09-11

申请号：US12431874

申请日：2009-04-29

申请人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

发明人： Guhan Krishnan ,  Antonio Asaro ,  Don Cherepacha ,  Thomas R. Kunjan ,  Joerg Winkler ,  Ralf Flemming ,  Maurice B. Steinman ,  Jonathan Owen ,  John Kalamatianos

IPC分类号： G06F13/18

CPC分类号： G06F13/161

摘要： A hierarchical memory request stream arbitration technique merges coherent memory request streams from multiple memory request sources and arbitrates the merged coherent memory request stream with requests from a non-coherent memory request stream. In at least one embodiment of the invention, a method of generating a merged memory request stream from a plurality of memory request streams includes merging coherent memory requests into a first serial memory request stream. The method includes selecting, by a memory controller circuit, a memory request for placement in the merged memory request stream from at least the first serial memory request stream and a merged non-coherent request stream. The merged non-coherent memory request stream is at least partially based on an indicator of a previous memory request selected for placement in the merged memory request stream.

摘要翻译： 分级存储器请求流仲裁技术将来自多个存储器请求源的相干存储器请求流合并，并且根据来自非相干存储器请求流的请求对合并的相干存储器请求流进行仲裁。 在本发明的至少一个实施例中，从多个存储器请求流生成合并存储器请求流的方法包括将相干存储器请求合并到第一串行存储器请求流中。 该方法包括由存储器控制器电路从至少第一串行存储器请求流和合并的非相干请求流中选择存储器请求，以供放置在合并的存储器请求流中。 合并的非相干存储器请求流至少部分地基于选择用于放置在合并的存储器请求流中的先前存储器请求的指示符。

公开(公告)号：US07957428B2

公开(公告)日：2011-06-07

申请号：US10850809

申请日：2004-05-21

申请人： Maurice B. Steinman ,  Rahul R. Shah ,  Naveen Cherukuri ,  Aaron T. Spink ,  Allen J. Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David S. Dunning ,  Theodore Z. Schoenborn

发明人： Maurice B. Steinman ,  Rahul R. Shah ,  Naveen Cherukuri ,  Aaron T. Spink ,  Allen J. Baum ,  Sanjay Dabral ,  Tim Frodsham ,  David S. Dunning ,  Theodore Z. Schoenborn

IPC分类号： H04J3/04

CPC分类号： G06F13/4018 ,  G06F13/4009 ,  Y02D10/14 ,  Y02D10/151

摘要： Embodiments of the invention provide an algorithm for dividing a link into one or more reduced-width links. For one embodiment of the invention, a multiplexing scheme is employed to effect a bit transmission order required by a particular cyclic redundancy check. The multiplexed output bits are then swizzled on-chip to reduce on-board routing congestion.

摘要翻译： 本发明的实施例提供了一种用于将链路划分成一个或多个缩小宽度链路的算法。 对于本发明的一个实施例，采用复用方案来实现特定循环冗余校验所需的位传输顺序。 多路复用的输出位随后在芯片上转动，以减少车载路由拥塞。

公开(公告)号：US07750912B2

公开(公告)日：2010-07-06

申请号：US11286690

申请日：2005-11-23

申请人： R. Stephen Polzin ,  Richard T. Witek ,  Maurice B. Steinman

发明人： R. Stephen Polzin ,  Richard T. Witek ,  Maurice B. Steinman

IPC分类号： G09G5/36

CPC分类号： G06F1/3293 ,  G06F1/3203 ,  G06F1/3218 ,  G06F1/325 ,  G06F15/7807 ,  Y02D10/122 ,  Y02D50/20

摘要： In one embodiment, a system comprises a memory; a memory interface coupled to the memory; a processor unit coupled to the memory interface, a second interface coupled to the processor unit, and a graphics processing unit. The processor unit comprises at least one processor core and a display controller configured to couple to a display. The graphics processing unit is configured to render data into a frame buffer representing an image to be displayed on the display. The processor unit is configured to deactivate the second interface if the graphics processing unit is not rendering, and the display controller is configured to read the frame buffer data for display even if the second interface is deactivated.

摘要翻译： 在一个实施例中，系统包括存储器; 耦合到存储器的存储器接口; 耦合到存储器接口的处理器单元，耦合到处理器单元的第二接口和图形处理单元。 处理器单元包括至少一个处理器核心和被配置为耦合到显示器的显示控制器。 图形处理单元被配置为将数据呈现到表示要在显示器上显示的图像的帧缓冲器。 如果图形处理单元不呈现，则处理器单元被配置为停用第二接口，并且即使第二接口被停用，显示控制器被配置为读取用于显示的帧缓冲器数据以进行显示。

公开(公告)号：US07200770B2

公开(公告)日：2007-04-03

申请号：US10750495

申请日：2003-12-31

申请人： David W. Hartwell ,  Maurice B. Steinman

发明人： David W. Hartwell ,  Maurice B. Steinman

IPC分类号： G06F11/00

CPC分类号： G06F11/073 ,  G06F11/076

摘要： A computer system comprising a memory system that comprises a plurality of memory modules; and a memory controller that accesses the plurality of memory modules to service memory requests. The computer system also comprises an error-type memory controller that configures the noted access such that the memory controller can continue to access a failed one of the plurality of memory modules that incurred a soft error.

摘要翻译： 一种计算机系统，包括包括多个存储器模块的存储器系统; 以及存储器控制器，其访问所述多个存储器模块以服务存储器请求。 计算机系统还包括错误类型的存储器控​​制器，其配置所述访问，使得存储器控制器可以继续访问引起软错误的多个存储器模块中的故障的存储器模块。

公开(公告)号：US09021209B2

公开(公告)日：2015-04-28

申请号：US12702085

申请日：2010-02-08

申请人： Alexander Branover ,  Maurice B. Steinman

发明人： Alexander Branover ,  Maurice B. Steinman

IPC分类号： G06F12/08

CPC分类号： G06F12/0808 ,  G06F1/3203 ,  G06F12/0831 ,  G06F2212/1028 ,  Y02D10/126 ,  Y02D10/13

摘要： A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.

摘要翻译： 处理节点跟踪与其高速缓存相关联的探测活动级别。 处理节点和/或处理系统进一步预测空闲持续时间。 如果探测器活动级别增加到高于阈值探测器活动级别，并且空闲持续时间预测高于阈值空闲持续时间阈值，则处理节点刷新其高速缓存以防止对高速缓存的探测。 如果探测器活动级别高于阈值探测器活动级别，但是预测的空闲持续时间太短，则处理节点的性能状态增加到高于其当前性能状态，以提供响应探测请求的增强的性能能力。

公开(公告)号：US08656198B2

公开(公告)日：2014-02-18

申请号：US12767460

申请日：2010-04-26

申请人： Alexander Branover ,  Maurice B. Steinman ,  Anthony Asaro ,  James B. Fry

发明人： Alexander Branover ,  Maurice B. Steinman ,  Anthony Asaro ,  James B. Fry

IPC分类号： G06F1/00

CPC分类号： G06F1/3203 ,  G06F1/3275 ,  G06F1/3287 ,  G11C5/148 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171 ,  Y02D50/20

摘要： A method for power management is disclosed. The method may include monitoring requests for access to a memory of a memory subsystem by one or more processor cores; and monitoring requests for access to the memory conveyed by an input/output (I/O) unit. The method may further include determining if at least a first amount of time has elapsed since any one of the processor cores has asserted a memory access request and determining if at least a second amount of time has elapsed since the I/O unit has conveyed a memory access request. A first signal may be asserted if the first and second amounts of time have elapsed. A memory subsystem may be transitioned from operating in a full power state to a first low power state responsive to assertion of the first signal.

摘要翻译： 公开了一种用于电力管理的方法。 该方法可以包括监视由一个或多个处理器核访问存储器子系统的存储器的请求; 以及监视对由输入/输出（I / O）单元传送的存储器的访问请求。 该方法还可以包括确定是否已经过去了至少第一时间量，因为处理器核心已经确定了存储器访问请求并且确定自I / O单元是否已经传送了至少第二时间量 内存访问请求。 如果第一和第二时间量已经过去，则可以断言第一信号。 存储器子系统可以响应于第一信号的断言而从全功率状态工作转变到第一低功率状态。

公开(公告)号：US20120324258A1

公开(公告)日：2012-12-20

申请号：US13162425

申请日：2011-06-16

申请人： Alexander BRANOVER ,  Maurice B. Steinman

发明人： Alexander BRANOVER ,  Maurice B. Steinman

IPC分类号： G06F1/32 ,  G06F1/00

CPC分类号： G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D10/151

摘要： A method of regulating power states in a processing system may begin with a processor component reporting a present processor power state to an input-output hub, where the present processor power state corresponds to one of a plurality of different processor power states ranging from an active state to an inactive state. The input-output hub receives data indicative of the present processor power state and, in response to receiving the present processor power state, establishes a lowest allowable hub power state that corresponds to one of a plurality of different hub power states ranging from an active state to an inactive state. The method continues by determining a present hub power state for the input-output hub, wherein depth of the present hub power state is less than or equal to depth of the lowest allowable hub power state.

摘要翻译： 调节处理系统中的功率状态的方法可以从将当前处理器功率状态报告给输入 - 输出集线器的处理器组件开始，其中当前处理器功率状态对应于多个不同的处理器功率状态中的一个， 状态为非活动状态。 输入 - 输出集线器接收指示当前处理器功率状态的数据，并且响应于接收到当前处理器功率状态，建立对应于多个不同集线器功率状态中的一个的最低可允许集线器功率状态，该状态从活动状态 到非活动状态。 该方法通过确定用于输入 - 输出集线器的当前集线器功率状态来继续，其中当前集线器功率状态的深度小于或等于最低可允许集线器功率状态的深度。