公开(公告)号：US20090180341A1

公开(公告)日：2009-07-16

申请号：US12314860

申请日：2008-12-17

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： G11C7/00 ,  H03L7/06 ,  G11C8/18

CPC分类号： G11C7/22 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/12 ,  G11C7/20 ,  G11C7/222 ,  G11C11/4094 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10897 ,  H03K5/15066

摘要： Disclosed is a semiconductor device including a first clock generator that generates a first clock signal having a first period from an input clock signal, a second clock generator that generates a second clock signal having a second period from the input clock signal, and a timing generator that receives the first clock signal, the second clock signal, an activation signal from a command decoder and a selection signal for selecting the delay time from a timing register to produce a timing signal delayed as from activation of the activation signal by a delay equal to a sum of a time equal to a preset number m prescribed by the selection signal times the first period and a time equal to another preset number n prescribed by the selection signal times the second period. The timing register holds the values of m and n. These values are set in the timing register in an initialization sequence at the time of a mode register set command. In the operating states, the timing signals are output from the timing generator at a desired timing based on the information stored in the timing register (FIG. 6).

摘要翻译： 公开了一种半导体器件，包括第一时钟发生器，其从输入时钟信号产生具有第一周期的第一时钟信号;第二时钟发生器，其从输入时钟信号产生具有第二周期的第二时钟信号;以及定时发生器 其接收第一时钟信号，第二时钟信号，来自命令解码器的激活信号和用于从定时寄存器选择延迟时间的选择信号，以产生从激活信号的激活延迟等于 等于由选择信号规定的预定数量m的时间等于第一周期的时间和等于由选择信号规定的另一个预设数量n的时间乘以第二周期的时间之和。 定时寄存器保存m和n的值。 这些值在模式寄存器设置命令时以初始化顺序设置在定时寄存器中。 在操作状态下，基于定时寄存器（图6）中存储的信息，定时信号以定时发生器输出。

公开(公告)号：US07224629B2

公开(公告)日：2007-05-29

申请号：US11071351

申请日：2005-03-04

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pulldown circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US20060200727A1

公开(公告)日：2006-09-07

申请号：US11194486

申请日：2005-08-02

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Tomonori Sekiguchi

IPC分类号： G11C29/00

CPC分类号： G11C29/4401 ,  G11C11/401 ,  G11C29/42 ,  G11C29/44

摘要： When the miniaturization of a DRAM advances, the capacity of a cell capacitor decreases, and further the voltage of a data line is lowered, the amount of read signals remarkably lowers, errors are produced during readout, and the yield of chips lowers. To solve the above problems, the present invention provides a DRAM that: has an error correcting code circuit for each sub-array; detects and corrects errors with said error correcting code circuit in both the reading and writing operations; and further has rescue circuits in addition to said error correcting code circuits and replaces a defective cell caused by hard error with a redundant bit.

公开(公告)号：US08199596B2

公开(公告)日：2012-06-12

申请号：US12939069

申请日：2010-11-03

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US07772911B2

公开(公告)日：2010-08-10

申请号：US12208978

申请日：2008-09-11

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C19/00

摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.

摘要翻译： 公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从 第一时钟信号的上升沿大约为td = m·T1 + n·（T2 / L）的延迟td。 定时控制电路包括粗延迟电路和精细延迟电路。 粗略延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量大约为m·T1的粗略定时信号。 精细延迟电路包括L个并联设置的多相时钟控制延迟电路，通过n·T2 / L延迟由L组第二时钟组的相应时钟对粗略定时信号进行采样的定时， 或者产生延迟脉冲，从而产生精细定时信号。

公开(公告)号：US20090146716A1

公开(公告)日：2009-06-11

申请号：US12314207

申请日：2008-12-05

申请人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

发明人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

IPC分类号： H03H11/26

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C19/00 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03K2005/00241

摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

摘要翻译： 定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟 延迟元件 定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。 粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。 精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。 定时信号延迟的变化减小。

公开(公告)号：US20080054262A1

公开(公告)日：2008-03-06

申请号：US11771779

申请日：2007-06-29

申请人： Hiroaki Nakaya ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura

发明人： Hiroaki Nakaya ,  Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura

IPC分类号： H01L23/58

CPC分类号： G11C5/146 ,  G11C11/401 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  H01L2924/0002 ,  H01L2924/00

摘要： A substrate voltage control technique that prevents the operating speed from being decreased and suppresses a leakage current due to a lower threshold voltage with respect to a low voltage use. Since a center value of the threshold voltages is detected by plural replica MOS transistors, and a substrate voltage is controlled to control a center value of the threshold voltages, thereby making it possible to satisfy a lower limit of the operating speed and an upper limit of a leakage current of the entire chip. On the other hand, the substrate voltage is dynamically controlled during the operation of the chip, thereby making it possible to decrease the center value of the threshold voltages when the chip operates to improve the speed, and to increase the center value of the threshold voltages after the operation of the chip to reduce the leakage current of the entire chip.

摘要翻译： 一种防止工作速度降低的基板电压控制技术，并且相对于低电压使用而抑制由于阈值电压较低导致的漏电流。 由于通过多个复制MOS晶体管检测阈值电压的中心值，并且控制衬底电压以控制阈值电压的中心值，从而可以满足操作速度的下限和上限 整个芯片的漏电流。 另一方面，在芯片工作期间动态地控制衬底电压，从而可以在芯片工作时降低阈值电压的中心值以提高速度，并且增加阈值电压的中心值 芯片运行后降低整个芯片的漏电流。

公开(公告)号：US20050232044A1

公开(公告)日：2005-10-20

申请号：US11071351

申请日：2005-03-04

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： H01L21/8242 ,  G11C7/02 ,  G11C7/06 ,  G11C11/401 ,  G11C11/409 ,  G11C11/4091 ,  H01L27/108

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： Due to the further scaling down, the offset of the sense amplifier is increased and the malfunction occurs in the read operation, and thus, the yield of the chip is degraded. For its prevention, a plurality of pull-down circuits and one pull-up circuit are used to constitute the sense amplifier circuit. Also, the transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of the transistor in the other pull-down circuit. Further, the pull-down circuit with a larger constant of the transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 由于进一步缩小，读取放大器的偏移增加，并且在读取操作中发生故障，因此芯片的产量降低。 为了防止，使用多个下拉电路和一个上拉电路来构成读出放大器电路。 此外，多个下拉电路之一中的晶体管具有诸如沟道长度或沟道宽度等于另一个下拉电路中的晶体管的沟道宽度的常数。 此外，首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US20110079858A1

公开(公告)日：2011-04-07

申请号：US12967728

申请日：2010-12-14

申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

IPC分类号： H01L27/108

CPC分类号： G11C11/4091 ,  H01L27/10897

摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

摘要翻译： 具有高集成度，低功耗和高操作速度的半导体存储器件。 存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。 构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。 具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。 数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

公开(公告)号：US07843751B2

公开(公告)日：2010-11-30

申请号：US12352347

申请日：2009-01-12

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。