公开(公告)号：US20110079858A1

公开(公告)日：2011-04-07

申请号：US12967728

申请日：2010-12-14

申请人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

发明人： Satoru Akiyama ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

IPC分类号： H01L27/108

CPC分类号： G11C11/4091 ,  H01L27/10897

摘要： A semiconductor memory device having high integration, low power consumption and high operation speed. The memory device includes a sense amplifier circuit having plural pull-down circuits and a pull-up circuit. A transistor constituting one of the plural pull-down circuits has a larger constant than that of a transistor constituting the other pull-down circuits, for example, a channel length and a channel width. The pull-down circuit having the larger constant transistor is activated earlier than the other pull-down circuits and the pull-up circuit, which are activated to conduct reading. The data line and the earlier driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

摘要翻译： 具有高集成度，低功耗和高操作速度的半导体存储器件。 存储器件包括具有多个下拉电路和上拉电路的读出放大器电路。 构成多个下拉电路中的一个的晶体管具有比构成其它下拉电路的晶体管的常数更大的常数，例如沟道长度和沟道宽度。 具有较大恒定晶体管的下拉电路比另一个下拉电路和上拉电路更早启动，这些电路被激活以进行读取。 数据线和较早驱动的下拉电路由NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制下拉电路的激活或失活。

公开(公告)号：US07843751B2

公开(公告)日：2010-11-30

申请号：US12352347

申请日：2009-01-12

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US07750712B2

公开(公告)日：2010-07-06

申请号：US12314207

申请日：2008-12-05

申请人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

发明人： Akira Ide ,  Yasuhiro Takai ,  Akira Kotabe ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama

IPC分类号： H03H11/26

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C19/00 ,  H03K5/131 ,  H03K5/14 ,  H03K2005/00058 ,  H03K2005/00241

摘要： A timing control circuit DLY1 receives clock signal CKa with period T1 and activation signal ACT and outputs fine timing signal FT with delay of m*T1+tda measured from the clock signal where m denotes a non-negative integer and tda denotes delay in the analog delay element. The timing control circuit DLY1 comprises a coarse delay circuit CD and a fine delay circuit FD. The coarse delay circuit CD comprises a counter for counting a rising edge of the clock signal CKa after receiving activation signal ACT and outputs coarse timing signal CT with delay of m*T1 measured from a rising edge of the clock signal CKa. The fine delay circuit FD comprises a plurality of analog delay elements and outputs fine delay timing signal FT with delay of tda measured from the coarse timing signal CT. Variation in delay of timing signal is reduced.

摘要翻译： 定时控制电路DLY1接收具有周期T1和激活信号ACT的时钟信号CKa，并从m表示非负整数的时钟信号输出延迟m * T1 + tda的精确定时信号FT，并且tda表示模拟 延迟元件 定时控制电路DLY1包括粗延迟电路CD和精细延迟电路FD。 粗延迟电路CD包括用于在接收到激活信号ACT之后对时钟信号CKa的上升沿进行计数的计数器，并输出从时钟信号CKa的上升沿测量的具有延迟m * T1的粗定时信号CT。 精细延迟电路FD包括多个模拟延迟元件，并输出从粗定时信号CT测得的具有延迟tda的精细延迟定时信号FT。 定时信号延迟的变化减小。

公开(公告)号：US07633833B2

公开(公告)日：2009-12-15

申请号：US12028788

申请日：2008-02-09

申请人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

发明人： Riichiro Takemura ,  Tomonori Sekiguchi ,  Satoru Akiyama ,  Hiroaki Nakaya ,  Masayuki Nakamura

IPC分类号： G11C8/00

CPC分类号： G11C7/04 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C2207/2272

摘要： The semiconductor memory device according to the invention is provided with a first delay circuit block that generates a timing signal of a circuit block to be operated in column cycle time determined by an external input command cycle and a second delay circuit block the whole delay of which is controlled to be a difference between access time determined by an external clock and the latency and column cycle time. These delay circuit blocks are controlled so that the delay of each delay circuit is a suitable value in accordance with column latency and an operating frequency, and each delay is controlled corresponding to dispersion in a process and operating voltage and a change of operating temperature.

摘要翻译： 根据本发明的半导体存储器件具有第一延迟电路块，该第一延迟电路块产生在由外部输入指令周期确定的列周期时间内操作的电路块的定时信号，而第二延迟电路阻止其整个延迟 被控制为由外部时钟确定的访问时间与延迟和列周期时间之间的差异。 控制这些延迟电路块，使得每个延迟电路的延迟是根据列等待时间和工作频率的合适值，并且根据工艺中的色散和工作电压以及工作温度的变化控制每个延迟。

公开(公告)号：US07505299B2

公开(公告)日：2009-03-17

申请号：US11976531

申请日：2007-10-25

申请人： Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Tomonori Sekiguchi ,  Kazuhiko Kajigaya

发明人： Riichiro Takemura ,  Satoru Akiyama ,  Satoru Hanzawa ,  Tomonori Sekiguchi ,  Kazuhiko Kajigaya

IPC分类号： G11C5/06 ,  G11C11/24 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10873

摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.

摘要翻译： 提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。 晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。 当访问存储器单元时，两个晶体管被激活并且读取该信息。 当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

公开(公告)号：US20080175084A1

公开(公告)日：2008-07-24

申请号：US11969223

申请日：2008-01-03

申请人： Satoru AKIYAMA ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

发明人： Satoru AKIYAMA ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Hiroaki Nakaya ,  Shinichi Miyatake ,  Yuko Watanabe

IPC分类号： G11C7/06

CPC分类号： G11C11/4091 ,  H01L27/10897

摘要： A semiconductor memory device having high integration, low consumption power and high operation speed compatible to each other including a sense amplifier circuit having plural pull-down circuits and a pull-up circuit, in which a transistor constituting one of plural pull-down circuits has a larger constant than that of a transistor constituting other pull-down circuits, for example, a channel length and a channel width, a pull-down circuit having a larger constant of the transistor in the plural pull-down circuits is precedingly activated and then another pull-down circuit and the pull-up circuit are activated to conduct reading and, further, the data line and the precedingly driven pull-down circuit are connected by an NMOS transistor and the NMOS transistor is activated or inactivated to control the activation or inactivation of the pull-down circuit.

摘要翻译： 一种具有高集成度，低功耗和高运行速度的半导体存储器件，包括具有多个下拉电路和上拉电路的读出放大器电路，其中构成多个下拉电路中的一个的晶体管具有 比构成其他下拉电路的晶体管（例如沟道长度和沟道宽度）的常数大的常数，在多个下拉电路中具有较大的晶体管常数的下拉电路先前被激活，然后 另一个下拉电路和上拉电路被激活以进行读取，此外，数据线和先前驱动的下拉电路通过NMOS晶体管连接，并且NMOS晶体管被激活或失活以控制激活或 下拉电路失活。

公开(公告)号：US20080017904A1

公开(公告)日：2008-01-24

申请号：US11773990

申请日：2007-07-06

申请人： Satoru AKIYAMA ,  Ryuta Tsuchiya ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Masayuki Nakamura ,  Yasushi Yamazaki ,  Shigeru Shiratake

发明人： Satoru AKIYAMA ,  Ryuta Tsuchiya ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Masayuki Nakamura ,  Yasushi Yamazaki ,  Shigeru Shiratake

IPC分类号： H01L27/108 ,  H01L21/8242

CPC分类号： H01L27/10894 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L2924/0002 ,  H01L2924/00

摘要： A DRAM capable of realizing reduced power consumption, high-speed operation, and high reliability is provided. A gate electrode configuring a memory cell transistor of the DRAM is composed of an n-type polysilicon film and a W (tungsten) film stacked thereon. A part of the polysilicon film is embedded in a trench formed in a silicon substrate in order to elongate the effective channel length of the memory cell transistor. The other part of the polysilicon film is located above the trench, and an upper surface thereof is located above a surface of the silicon substrate (p-type well). Therefore, distances between the W film and a source and drain (n-type semiconductor regions) are ensured.

摘要翻译： 提供了能够实现降低功耗，高速运行和高可靠性的DRAM。 构成DRAM的存储单元晶体管的栅电极由n型多晶硅膜和堆叠在其上的W（钨）膜构成。 为了延长存储单元晶体管的有效沟道长度，多晶硅膜的一部分嵌入在硅衬底中形成的沟槽中。 多晶硅膜的另一部分位于沟槽上方，其上表面位于硅衬底的表面上方（p型阱）。 因此，确保W膜与源极和漏极（n型半导体区域）之间的距离。

公开(公告)号：US20060158924A1

公开(公告)日：2006-07-20

申请号：US11280170

申请日：2005-11-17

申请人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

发明人： Tomonori Sekiguchi ,  Satoru Akiyama ,  Riichiro Takemura ,  Satoru Hanzawa ,  Kazuhiko Kajigaya

IPC分类号： G11C11/24

CPC分类号： G11C11/4094 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4074 ,  G11C11/4097 ,  G11C2211/4013 ,  H01L27/0207 ,  H01L27/10882

摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.

摘要翻译： 从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压 晶体管经由存储单元晶体管写入电容器的存储节点。 此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且 根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

公开(公告)号：US08199596B2

公开(公告)日：2012-06-12

申请号：US12939069

申请日：2010-11-03

申请人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

发明人： Satoru Akiyama ,  Riichiro Takemura ,  Takayuki Kawahara ,  Tomonori Sekiguchi

IPC分类号： G11C7/02

CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C2207/065 ,  H01L27/10897

摘要： A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality of pull-down circuits and a pull-up circuit, and a transistor in one of the plurality of pull-down circuits has a constant such as a channel length or a channel width larger than that of a transistor in another pull-down circuit. The pull-down circuit with a larger constant of a transistor is first activated, and then, the other pull-down circuit and the pull-up circuit are activated to perform the read operation.

摘要翻译： 构造读出放大器以减少存储器读取操作中的故障的发生，并因此由于读出放大器随着进一步的封闭而增加偏移而降低了芯片产量。 读出放大器电路由多个下拉电路和上拉电路构成，并且多个下拉电路之一中的晶体管具有常数，例如通道长度或通道宽度大于 另一个下拉电路中的晶体管。 首先激活具有较大的晶体管常数的下拉电路，然后激活另一个下拉电路和上拉电路以执行读取操作。

公开(公告)号：US07772911B2

公开(公告)日：2010-08-10

申请号：US12208978

申请日：2008-09-11

申请人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

发明人： Akira Ide ,  Yasuhiro Takai ,  Tomonori Sekiguchi ,  Riichiro Takemura ,  Satoru Akiyama ,  Hiroaki Nakaya

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  G11C7/04 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/4076 ,  G11C19/00

摘要： Disclosed is a timing control circuit that receives a first clock having a period T1, a group of second clocks of L different phases spaced apart from each other at substantially equal intervals and selection signals m, n supplied thereto and generates a fine timing signal delayed from the rising edge of the first clock signal by a delay td of approximately td=m·T1+n·(T2/L). The timing control circuit includes a coarse delay circuit and a fine delay circuit. The coarse delay circuit includes a counter for counting a rising edge of the first clock signal after an activate signal is activated and generates a coarse timing signal whose amount of delay from the first clock signal is approximately m·T1. The fine delay circuit comprises L-number of multiphase clock control delay circuits disposed in parallel, delays by n·T2/L the timing of sampling of the coarse timing signal by respective clocks of the group of L-phase second clocks, and takes the OR among the resulting delayed pulses to thereby produce the fine timing signal.

摘要翻译： 公开了一种定时控制电路，其接收具有周期T1的第一时钟，以相等间隔彼此间隔开的L个不同相位的一组第二时钟，以及提供给其的选择信号m，n，并产生从 第一时钟信号的上升沿大约为td = m·T1 + n·（T2 / L）的延迟td。 定时控制电路包括粗延迟电路和精细延迟电路。 粗略延迟电路包括用于在激活信号被激活之后对第一时钟信号的上升沿进行计数的计数器，并产生其第一时钟信号的延迟量大约为m·T1的粗略定时信号。 精细延迟电路包括L个并联设置的多相时钟控制延迟电路，通过n·T2 / L延迟由L组第二时钟组的相应时钟对粗略定时信号进行采样的定时， 或者产生延迟脉冲，从而产生精细定时信号。