公开(公告)号：US06868482B1

公开(公告)日：2005-03-15

申请号：US09506038

申请日：2000-02-17

申请人： Donald W. Mackenthun ,  Mitchell A. Bauman ,  Donald C. Englin

发明人： Donald W. Mackenthun ,  Mitchell A. Bauman ,  Donald C. Englin

IPC分类号： G06F12/08 ,  G06F11/16

CPC分类号： G06F12/0804 ,  G06F12/0811 ,  G06F12/0891

摘要： Each dual multi-processing system has a number of processors, with each processor having a store in first-level write through cache to a second-level cache. A third-level memory is shared by the dual system with the first-level and second-level caches being globally addressable to all of the third-level memory. Processors can write through to the local second-level cache and have access to the remote second-level cache via the local storage controller. A coherency scheme for the dual system provides each second-level cache with indicators for each cache line showing which ones are valid and which ones have been modified or are different than what is reflected in the corresponding third level memory. The flush apparatus uses these two indicators to transfer all cache lines that are within the remote memory address range and have been modified, back to the remote memory prior to dynamically removing the local cache resources due to either system maintenance or dynamic partitioning.

摘要翻译： 每个双重多处理系统具有多个处理器，每个处理器具有通过缓存的第一级写入到第二级缓存的存储。 第三级存储器由双系统共享，第一级和第二级高速缓存可全局寻址到所有第三级存储器。 处理器可以写入本地二级缓存，并通过本地存储控制器访问远程二级缓存。 双系统的一致性方案为每个二级缓存提供每个高速缓存行的指示符，其中显示哪些是有效的，哪些已被修改或不同于相应的第三级存储器中反映的指示。 冲洗装置使用这两个指示器将在远程存储器地址范围内的所有高速缓存行传送到远程存储器，然后由于系统维护或动态分区而动态地删除本地缓存资源。

公开(公告)号：US06799252B1

公开(公告)日：2004-09-28

申请号：US09774833

申请日：2001-01-31

申请人： Mitchell A. Bauman

发明人： Mitchell A. Bauman

IPC分类号： G06F1200

CPC分类号： G06F12/0817 ,  G06F12/0813 ,  G06F13/4022

摘要： A modular, expandable, multi-port main memory system that includes multiple point-to-point switch interconnections and a highly-parallel data path structure that allows multiple memory operations to occur simultaneously. The main memory system includes an expandable number of modular Memory Storage Units, each of which are mapped to a portion of the total address space of the main memory system, and may be accessed simultaneously. Each of the Memory Storage Units includes a predetermined number of memory ports, and an expandable number of memory banks, wherein each of the memory banks may be accessed simultaneously. Each of the memory banks is also modular, and includes an expandable number of memory devices each having a selectable memory capacity. All of the memory devices in the system may be performing different memory read or write operations substantially simultaneously and in parallel. Multiple data paths within each of the Memory Storage Units allow data transfer operations to occur to each of the multiple memory ports in parallel. Simultaneously with the transfer operations occurring to the memory ports, unrelated data transfer operations may occur to multiple ones of the memory devices within all memory banks in parallel. The main memory system further incorporates independent storage devices and control logic to implement a directory-based coherency protocol. Thus the main memory system is adapted to providing the flexibility, bandpass, and memory coherency needed to support a high-speed multiprocessor environment.

摘要翻译： 一种模块化，可扩展的多端口主存储系统，包括多个点对点交换机互连以及允许多个存储器操作同时发生的高度并行数据路径结构。 主存储器系统包括可扩展数量的模块化存储器单元，每个存储单元被映射到主存储器系统的总地址空间的一部分，并且可以被同时访问。 每个存储器存储单元包括预定数量的存储器端口和可扩展数量的存储器组，其中可以同时访问每个存储器组。 每个存储体也是模块化的，并且包括每个具有可选存储器容量的可扩展数量的存储器件。 系统中的所有存储器件可以基本同时并行地执行不同的存储器读或写操作。 每个内存存储单元内的多个数据路径允许数据传输操作并行地发生到多个存储器端口中的每一个。 与存储器端口发生的传送操作同时，并行地在所有存储器组中的多个存储器件中可能发生不相关的数据传输操作。 主存储系统还包括独立的存储设备和控制逻辑，以实现基于目录的一致性协议。 因此，主存储器系统适于提供支持高速多处理器环境所需的灵活性，带通和存储器一致性。

公开(公告)号：US06457101B1

公开(公告)日：2002-09-24

申请号：US09468050

申请日：1999-12-20

申请人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Donald R. Kalvestrand ,  Joseph S. Schibinger ,  Daniel S. Tokoly

发明人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Donald R. Kalvestrand ,  Joseph S. Schibinger ,  Daniel S. Tokoly

IPC分类号： G06F1208

CPC分类号： G06F12/0817 ,  G06F12/0811 ,  G06F12/0862 ,  G06F2212/507

摘要： A hierarchical memory structure includes a directory-based main memory coupled to multiple first storage devices, each to store data signals retrieved from the main memory. Ones of the first storage devices are further respectively coupled to second storage devices, each to store data signals retrieved from the respectively coupled first storage devices. Fetch requests to retrieve data signals are issued by ones of the storage devices to the main memory. In response, the main memory determines where the most recent data copy resides, and issues a return request, if necessary to retrieve that copy for the requesting storage device. A speculative return generation logic circuit is coupled to at least two of the first storage devices to intercept the fetch requests. In response to an intercepted request, the speculative return generation logic circuit generates a speculative return request directly to one or more of the other coupled first storage devices. This speculative return request causes any updated copies of the requested data signals that may be stored at a lower level in the hierarchical memory, to be transferred to the first storage device. If a return request for the data is then issued by the main memory in response to the fetch request, the requested data signals are resident in a first storage device, and are readily available to the main memory.

摘要翻译： 分层存储器结构包括耦合到多个第一存储设备的基于目录的主存储器，每个存储器件用于存储从主存储器检索的数据信号。 第一存储设备的另外分别耦合到第二存储设备，每个存储设备存储从分别耦合的第一存储设备检索的数据信号。 获取数据信号的请求由存储设备中的一个发送到主存储器。 作为响应，主存储器确定最近的数据副本所在的位置，并且如果需要检索请求存储设备的该副本，则发出返回请求。 推测返回生成逻辑电路耦合到至少两个第一存储设备以拦截提取请求。 响应于被截取的请求，推测返回产生逻辑电路直接向一个或多个其它耦合的第一存储设备产生推测返回请求。 该推测返回请求使得可以存储在分层存储器中的较低级的所请求的数据信号的任何更新的副本被传送到第一存储设备。 如果主存储器响应于提取请求发出对数据的返回请求，则所请求的数据信号驻留在第一存储设备中，并且容易对主存储器可用。

公开(公告)号：US06434641B1

公开(公告)日：2002-08-13

申请号：US09322405

申请日：1999-05-28

申请人： Michael L. Haupt ,  Mitchell A. Bauman

发明人： Michael L. Haupt ,  Mitchell A. Bauman

IPC分类号： G06F1208

CPC分类号： G06F12/0828 ,  G06F2212/621

摘要： A memory request management system for use with a memory system employing a directory-based cache coherency scheme is disclosed. The memory system includes a main memory coupled to receive requests from multiple cache memories. Directory-based logic is used to determine that some requests presented to the main memory can not be completed immediately because the most recent copy of the requested data must be retrieved from another cache memory. These requests are stored in a temporary storage structure and identified as “deferred” requests. Subsequently, predetermined ones of the memory requests that are requesting access to the same main memory address as is being requested by any deferred request are also deferred. When a data retrieval operation is completed, an associated request is designated as undeferred so that processing for that request may be completed, and the request may be removed from the temporary storage structure. According to one aspect of the invention, all deferred requests requesting access to the same main memory address are stored as a linked list of requests in the temporary storage structure. Requests are processed by main memory in a first-in, first-out manner such that the oldest requests are completed before more recently-received requests. According to another aspect of the invention, the request management system further handles I/O overwrite operations wherein a peripheral device is allowed to overwrite requested addresses within the main memory even though the most recent copy of the data associated with some of the overwritten memory addresses is stored within ones of the cache memories. To process the I/O overwrite operations in a manner that preserves data coherency, the I/O overwrite requests are deferred in a manner that is similar to cache-initiated requests. Specifically, I/O overwrite requests made to an address associated with any previously-deferred I/O overwrite or cache-initiated requests are deferred until all such previously-deferred requests are processed by main memory.

公开(公告)号：US06415364B1

公开(公告)日：2002-07-02

申请号：US09001588

申请日：1997-12-31

申请人： Mitchell A. Bauman ,  Eugene A. Rodi

发明人： Mitchell A. Bauman ,  Eugene A. Rodi

IPC分类号： G06F1206

CPC分类号： G06F12/0817

摘要： A high-speed memory system is disclosed for use in supporting a directory-based cache coherency protocol. The memory system includes at least one data system for storing data, and a corresponding directory system for storing the corresponding cache coherency information. Each data storage operation involves a block transfer operation performed to multiple sequential addresses within the data system. Each data storage operation occurs in conjunction with an associated read-modify-write operation performed on cache coherency information stored within the corresponding directory system. Multiple ones of the data storage operations may be occurring within one or more of the data systems in parallel. Likewise, multiple ones of the read-modify-write operations may be performed to one or more of the directory systems in parallel. The transfer of address, control, and data signals for these concurrently performed operations occurs in an interleaved manner. The use of block transfer operations in combination with the interleaved transfer of signals to memory systems prevents the overhead associated with the read-modify-write operations from substantially impacting system performance. This is true even when data and directory systems are implemented using the same memory technology.

摘要翻译： 公开了一种用于支持基于目录的高速缓存一致性协议的高速存储器系统。 存储器系统包括用于存储数据的至少一个数据系统和用于存储对应的高速缓存一致性信息的相应目录系统。 每个数据存储操作涉及对数据系统内的多个连续地址执行的块传送操作。 每个数据存储操作结合对相应目录系统中存储的高速缓存一致性信息执行的关联读 - 修改 - 写操作进行。 多个数据存储操作可以并行地在一个或多个数据系统内进行。 同样地，并行地对一个或多个目录系统执行多个读 - 修改 - 写操作。 这些并发执行的操作的地址，控制和数据信号的传送以交错的方式发生。 使用块传送操作与对存储器系统的信号的交错传送相结合，防止与读取 - 修改 - 写入操作相关联的开销基本上影响系统性能。 即使使用相同的内存技术来实现数据和目录系统，这一点也是如此。

公开(公告)号：US06381715B1

公开(公告)日：2002-04-30

申请号：US09223850

申请日：1998-12-31

申请人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Eugene A. Rodi

发明人： Mitchell A. Bauman ,  Roger L. Gilbertson ,  Eugene A. Rodi

IPC分类号： G11C2900

CPC分类号： G11C29/56 ,  G11C29/26 ,  G11C29/48

摘要： A system and method for testing and initializing a memory including multiple memory banks or a memory module partitioned into logical memory units. A plurality of memory exerciser testers are provided, one for each of the plurality of memory banks. Each of the memory exerciser testers includes an address generator to generate a sequence of memory bank addresses to successively address each of the memory banks in a cyclic manner, while each of the address generators concurrently addresses a different one of the memory banks. A data pattern generator is coupled to a corresponding one of the address generators to receive a data pattern control signal upon each output of each of the memory bank addresses generated by its corresponding address generator. The data pattern generator outputs a unique data pattern to the memory bank identified by the memory bank address in response to each occurrence of the data pattern control signal. A plurality of address initialization registers are provided, one for each of the plurality of exerciser testers. Each of the address initialization registers stores an initial memory bank address for one of the memory banks such that each of the address generators is preset to initially address a different one of the memory banks. In this manner, each memory bank is addressed by a different one of the address generators at any given time, which provides for concurrent testing of all memory banks and memory interfaces.

摘要翻译： 一种用于测试和初始化存储器的系统和方法，所述存储器包括多个存储体或分为逻辑存储单元的存储器模块。 提供了多个存储器练习器测试器，一个用于多个存储体中的每一个。 每个存储器练习器测试器包括地址发生器，以产生一系列存储体地址，以循环方式连续寻址每个存储体，同时每个地址生成器同时寻址不同的存储体。 数据模式发生器耦合到对应的一个地址发生器，以在由其对应的地址发生器产生的每个存储体地址的每个输出上接收数据模式控制信号。 响应于数据模式控制信号的每次出现，数据模式发生器将唯一的数据模式输出到由存储体地址识别的存储体。 提供了多个地址初始化寄存器，其中一个用于多个锻炼测试器中的每一个。 每个地址初始化寄存器存储用于存储器组之一的初始存储体地址，使得每个地址生成器被预设为最初寻址不同的存储体。 以这种方式，每个存储体在任何给定时间由不同的地址生成器寻址，这提供了对所有存储体和存储器接口的并行测试。

公开(公告)号：US06279098B1

公开(公告)日：2001-08-21

申请号：US08767455

申请日：1996-12-16

申请人： Mitchell A. Bauman ,  Lewis A. Boone ,  Donald E. Schroeder

发明人： Mitchell A. Bauman ,  Lewis A. Boone ,  Donald E. Schroeder

IPC分类号： G06F1500

CPC分类号： G06F9/5077

摘要： A method and apparatus for providing for serially transmitting partitioning information between system partitions, and between system partitions and the corresponding data processing resources. Serial transmission may allow the partitioning information to be transmitted using a single I/O ASIC pin, and a single PC board trace. In addition to reducing the required number of I/O ASIC pins and PC board traces, the present invention may increase the overall reliability of the partitioning mechanism.

摘要翻译： 一种用于在系统分区之间以及在系统分区与相应的数据处理资源之间串行发送分区信息的方法和装置。 串行传输可以允许使用单个I / O ASIC引脚和单个PC板跟踪传输分区信息。 除了减少所需数量的I / O ASIC引脚和PC板迹线之外，本发明可以增加分区机构的整体可靠性。

公开(公告)号：US6055607A

公开(公告)日：2000-04-25

申请号：US773717

申请日：1996-12-23

申请人： Mitchell A. Bauman ,  James L. Federici

发明人： Mitchell A. Bauman ,  James L. Federici

IPC分类号： G06F13/18 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F13/18

摘要： A method of interfacing multiple requests using a request hold register, a multiplexer and a snapshot register with multiple requests directed into both the request hold register and a multiplexer which prevents forwarding the requests to the snapshot register if the snapshot register is not in a receiving condition but if the snapshot register is in a receiving condition allows the request to immediately enter snapshot register without having to wait for the next clock cycle.

摘要翻译： 一种使用请求保持寄存器，多路复用器和具有多个请求的快照寄存器来连接多个请求的方法，所述多个请求被引导到请求保持寄存器和多路复用器中，如果快照寄存器不处于接收状态，则该多路复用器防止将请求转发到快照寄存器 但如果快照寄存器处于接收状态，则允许请求立即输入快照寄存器，而不必等待下一个时钟周期。

公开(公告)号：US5625892A

公开(公告)日：1997-04-29

申请号：US363446

申请日：1994-12-22

申请人： Mitchell A. Bauman ,  Michael L. Haupt

发明人： Mitchell A. Bauman ,  Michael L. Haupt

IPC分类号： G06F1/32 ,  G06F11/34 ,  H04B7/005 ,  H04L1/18

CPC分类号： H04W52/267 ,  G06F1/32 ,  G06F11/3433 ,  G06F2201/81 ,  G06F2201/88 ,  H04L1/1854 ,  Y02B60/165 ,  Y02B60/50

摘要： A dynamic power consumption reduction apparatus for reducing power consumption by temporarily delaying multiple data transfer interfaces. Data transfer interfaces are only delayed in rare circumstances where an exceptionally high number of data transfers are occurring for a period of time. The number of active data transfer interfaces is monitored, and a count value is incremented or decremented depending on the number of active data transfer interfaces. If the count value reaches a threshold value, it indicates that the number of data transfers for a predetermined period of time is exceptionally high, and therefore power consumption is high. Where the number of data transfers is high for a predetermined period of time, delays are injected into the handshake cycle to delay return of data acknowledge signals from data receivers to data transmitters. The delays are discontinued when the data transfer interface activity is reduced to a normal level. Hysteresis is provided to allow time for the power sourcing circuitry to recharge before discontinuing the delays.

摘要翻译： 一种用于通过临时延迟多个数据传输接口来降低功耗的动态功耗降低装置。 数据传输接口只有在极少数据数据传输一段时间的罕见情况下才被延迟。 监视活动数据传输接口的数量，根据活动数据传输接口的数量，计数值递增或递减。 如果计数值达到阈值，则表示预定时间段内的数据传输次数异常高，因此功耗高。 在预定时间段内数据传输数量高的情况下，将延迟注入到握手周期中，以将数据确认信号从数据接收器延迟到数据发送器。 当数据传输接口活动降低到正常水平时，延迟被停止。 提供迟滞，以便在停止延迟之前为供电电路充电的时间。

公开(公告)号：US20130132063A1

公开(公告)日：2013-05-23

申请号：US13299452

申请日：2011-11-18

申请人： Michael J. Rieschl ,  Mitchell A. Bauman ,  Feng-Jung Kao ,  Edward Lusienski ,  James R. McBreen ,  James F. Merten ,  Thomas L. Nowatzki ,  David W. Schroth ,  Scott L. Titus ,  Judge Yohn

发明人： Michael J. Rieschl ,  Mitchell A. Bauman ,  Feng-Jung Kao ,  Edward Lusienski ,  James R. McBreen ,  James F. Merten ,  Thomas L. Nowatzki ,  David W. Schroth ,  Scott L. Titus ,  Judge Yohn

IPC分类号： G06F9/455 ,  G06F9/45

CPC分类号： G06F9/4552 ,  G06F11/3624 ,  G06F11/3688

摘要： Systems and methods for testing and validation of translated memory banks used in an emulated system are disclosed. One method includes translating one or more banks of non-native instructions into one or more banks of native instructions executable in a computing system having a native instruction set architecture. The one or more banks of non-native instructions define one or more tests of execution of a non-native instruction set architecture. The method also includes loading a memory with instructions and data defined according to the non-native instruction set architecture and addressed by the one or more tests, and triggering, by an emulator, execution of the translated one or more banks of native instructions. The method further includes, upon detection of an error during execution of the translated one or more banks of native instructions, identifying an error in execution of the non-native instruction set architecture by the computing system.

摘要翻译： 公开了一种用于仿真系统中使用的翻译存储体的测试和验证的系统和方法。 一种方法包括将一组或多组非本地指令转换成具有本机指令集架构的计算系统中可执行的一个或多个本地指令库。 一个或多个非本机指令组定义了非本地指令集架构的一个或多个执行测试。 该方法还包括加载具有根据非本机指令集架构定义并由一个或多个测试寻址的指令和数据的存储器，以及由仿真器触发翻译的一个或多个本地指令库的执行。 该方法还包括：在执行翻译的一个或多个本机指令段期间检测到错误时，识别由计算系统执行非本地指令集架构的错误。