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21.发明授权公开(公告)号：US07042304B2
公开(公告)日：2006-05-09
申请号：US10705765
申请日：2003-11-10
IPC分类号： H04B3/00
CPC分类号： H03H11/0405 , H03H11/481
摘要： The invention relates to a circuit device for realizing a non-linear reactive elements scale network, wherein the non-linear elements of the network are pairs of inductive and capacitive components cascade connected between a pair of input terminals and a pair of output terminals. Advantageously in the invention, each component of the network is formed by cascade connecting a first and a second transconductance integrator with each other.
摘要翻译： 本发明涉及一种用于实现非线性无功元件规模网络的电路装置，其中网络的非线性元件是串联在一对输入端子和一对输出端子之间的电感和电容元件对。 在本发明中有利地，通过将第一和第二跨导积分器彼此级联连接来形成网络的每个部件。
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公开(公告)号：US06211705B1
公开(公告)日：2001-04-03
申请号：US09145732
申请日：1998-09-02
IPC分类号： H03K5153
CPC分类号： H03K3/356156
摘要： A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a “buffer” and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.
摘要翻译： 描述了一种定时双稳态电路，其包括两个逆变器，每个逆变器的输入连接到另一个的输出，经由“缓冲器”的输出和电路的输入经由受控的电子开关。 逆变器的电源端子通过另外两个受控开关连接到电路的电源端子。 时钟发生器提供定时信号以控制输入开关打开或关闭，并且当输入开关分别断开或闭合时，控制供电开关闭合或断开。 为了在比较频率高的比较器中获得可用于比较器的锁存器，通过在逆变器的电源端子和供电端子之间布置两个另外的电子开关，这两个电子开关由一个定时控制 信号以相对于输入开关闭合的预定延迟而闭合，并在输入开关断开时打开。
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23.发明授权Method and device for delaying selected transitions in a digital data stream 有权用于延迟数字数据流中所选择的转换的方法和装置公开(公告)号：US06208184B1
公开(公告)日：2001-03-27
申请号：US09451051
申请日：1999-11-30
IPC分类号： H03L700
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09
摘要： A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream. The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting the digital data stream from the second circuit directed to the write head. The transitions immediately following a preceding transition are delayed by the pre-established time interval, by sampling the two digital streams with a pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a certain different time interval.
摘要翻译： 提供了一种方法和电路，用于当在发生先前转换的时钟阶段发生转换时，将馈送到大容量存储设备的写入头的数字数据流中的转变延迟一定的时间间隔，以便 读取存储的数据时遇到的补偿前符号非线性干扰效应。 该方法包括将待存储的数字数据流和时钟信号馈送到第一电路，并从第一电路输出一对数字流。 每当在不连续输入流的转换的时钟相位的时钟相位期间，输入流的转变发生时，第一流假设第一逻辑值。 每当在输入流中发生转换的时钟相位之后的时钟相位期间，输入流的转变发生时，第二流假设第一逻辑值。 该方法还包括将两个数字流和时钟信号馈送到第二电路的输入，并从指向写入头的第二电路输出数字数据流。 通过用一对触发器对两个数字流进行采样来分别由分别延迟了某个不同的时间间隔的时钟信号定时，通过先前转换之后的转换被延迟预先建立的时间间隔。
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公开(公告)号：US5654675A
公开(公告)日：1997-08-05
申请号：US611831
申请日：1996-03-06
CPC分类号： H03L7/0891 , H03L7/099 , H03L7/107 , H03L2207/04 , H03L7/0995
摘要： A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.
摘要翻译： 具有改进的抖动特性的完全集成的锁相环（PLL）使用相同的数/模转换器（DAC），其通常用于控制低通环路滤波器的时间常数，以控制连接在输出端 压控振荡器和地的电压 - 电流转换输入级。 电容在循环传递函数中引入了第三极点。 以这种方式，传递函数的零和第三极之间的频域分离保持不变; 因此，阻尼因子保持恒定，同时PLL的ω0变化。
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25.发明授权公开(公告)号：US06750716B2
公开(公告)日：2004-06-15
申请号：US10162430
申请日：2002-06-03
IPC分类号： H03F345
CPC分类号： H03F3/45179 , H03F2203/45028 , H03F2203/45318 , H03F2203/45631
摘要： The amplifier circuit includes at least one amplification branch having an input transistor, an output transistor, having a source terminal connected to the input terminal and a drain terminal connected to a first output terminal, and a gain raising stage, having an input and an output connected to the source terminal and, respectively, to a gate terminal of the output transistor. The amplifier circuit includes, moreover, a compensation capacitor connected between the gate terminal and the drain terminal of the output transistor.
摘要翻译： 该放大器电路包括具有输入晶体管的至少一个放大支路，具有连接到输入端子的源极端子和连接到第一输出端子的漏极端子的输出晶体管以及具有输入和输出的增益提升级 分别连接到源极端子和输出晶体管的栅极端子。 此外，放大器电路还包括连接在输出晶体管的栅极端子和漏极端子之间的补偿电容器。
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26.发明授权Integrated circuit with two phase-locked loops and circuit for preventing locking owing to injection 失效具有两个锁相环的集成电路和用于防止注入锁定的电路
公开(公告)号：US6141313A
公开(公告)日：2000-10-31
申请号：US113576
申请日：1998-07-10
CPC分类号： H03L7/07 , G11B20/1403
摘要： An integrated circuit including two phase-locked loops each with its own oscillator. To prevent locking owing to injection between the two oscillators due to stray currents in the integrated circuit, a noise generator is coupled to the oscillator of one of the loops and a timer is provided for activating the noise generator in a manner such that the noise generated changes the frequency of the oscillator randomly when the other loop is in operation.
摘要翻译： 一个集成电路，包括两个锁相环，每个具有自己的振荡器。 为了防止由于集成电路中的杂散电流引起的两个振荡器之间的注入而导致的锁定，噪声发生器耦合到一个环路的振荡器，并且提供了定时器，以使得产生噪声的方式激活噪声发生器 当另一个循环运行时，随机振荡振荡器的频率。
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公开(公告)号：US6002542A
公开(公告)日：1999-12-14
申请号：US904599
申请日：1997-08-01
CPC分类号： G11B5/59688 , G11B5/59605 , G11B5/5534
摘要： A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the center of a recorded track. The servo-demodulator comprises a peak detector for successively and individually sampling the amplitude of each of a plurality of peaks of the pair of alternating signals, and a capacitor periodically connected to the output of the peak detector by a control logic for deriving a weighted average of the various successively sampled amplitudes. In this manner, the control logic obtains an averaged measure of amplitude with high immunity to noise.
摘要翻译： 一种用于由磁盘读取头产生的一对交替信号的伺服解调器，并且指示读取头相对于记录轨道的中心的位置。 伺服解调器包括峰值检测器，用于连续和单独地采样该对交变信号的多个峰值中的每一个的振幅;以及电容器，通过用于导出加权平均值的控制逻辑周期性地连接到峰值检测器的输出端 的各种连续采样幅度。 以这种方式，控制逻辑获得具有高抗噪声能力的幅度的平均测量值。
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28.发明授权VCO composed of plural ring oscillators and phase lock loop incorporating the VCO 失效VCO由多个环形振荡器和并入VCO的锁相环构成
公开(公告)号：US5864258A
公开(公告)日：1999-01-26
申请号：US846873
申请日：1997-05-01
CPC分类号： H03K3/013 , H03K3/0315 , H03L7/0995 , H03L7/183
摘要： A voltage-controlled oscillator, with high noise rejection of the supply voltage, includes a plurality of delay cells in an odd number N.gtoreq.3, which are connected to form a first ring oscillator and powered by the difference between a supply voltage Vcc and a variable regulating voltage VR. The VCO comprises at least one second ring oscillator formed by a plurality of delay cells in an odd number M.gtoreq.3, at least one of which is also a delay cell of the first oscillator and at least two of which do not belong to the first oscillator. At least one of these two cells is powered by a constant voltage (Vcc), in such a manner that the two oscillators operate at the same frequency and the interaction between the two oscillators introduces a high-frequency negative feedback which has the effect of effectively reducing the noise of the supply voltage Vcc.
摘要翻译： 具有电源电压的高噪声抑制的压控振荡器包括奇数N 3 / = 3中的多个延迟单元，其连接形成第一环形振荡器，并由电源电压Vcc 和可变调节电压VR。 VCO包括由奇数M> / = 3中的多个延迟单元形成的至少一个第二环形振荡器，其中至少一个延迟单元也是第一振荡器的延迟单元，并且其中至少两个不属于 第一个振荡器。 这两个电池中的至少一个由恒定电压（Vcc）供电，使得两个振荡器以相同的频率工作，并且两个振荡器之间的相互作用引入了具有有效效果的高频负反馈 降低电源电压Vcc的噪声。
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公开(公告)号：US5808488A
公开(公告)日：1998-09-15
申请号：US755466
申请日：1996-11-22
CPC分类号： H03K3/356156
摘要： A timed bistable circuit is described which includes two inverters each having its input connected to the output of the other, an output of the circuit via a "buffer" and an input of the circuit via a controlled electronic switch. The supply terminals of the inverters are connected to the supply terminals of the circuit via another two controlled switches. A clock generator provides timing signals to control both the input switches to open or close and to control the supply switches to close or open when the input switches are open or closed respectively. To obtain a latch usable in a comparator at a high comparison frequency the offset referred to the input is reduced and made independent of the frequency by arranging two further electronic switches between the supply terminals of the inverters and the supply terminals which are controlled by a timing signal in such a way as to close with a predetermined delay with respect to the closure of the input switches and to open when input switches open.
摘要翻译： 描述了一种定时双稳态电路，其包括两个逆变器，每个逆变器的输入连接到另一个的输出，经由“缓冲器”的输出和电路的输入经由受控的电子开关。 逆变器的电源端子通过另外两个受控开关连接到电路的电源端子。 时钟发生器提供定时信号以控制输入开关打开或关闭，并且当输入开关分别断开或闭合时，控制供电开关闭合或断开。 为了在比较频率高的比较器中获得可用于比较器的锁存器，通过在逆变器的电源端子和供电端子之间布置两个另外的电子开关，这两个电子开关由一个定时控制 信号以相对于输入开关闭合的预定延迟而闭合，并在输入开关断开时打开。
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30.发明授权
公开(公告)号：US5805022A
公开(公告)日：1998-09-08
申请号：US713715
申请日：1996-09-13
CPC分类号： H03G3/3026 , G11B5/02 , H03G1/0088
摘要： A circuit having a double half-wave rectifier connected to the outputs of a differential amplifier in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier. Two comparators each having an input are connected to an output of the rectifier and a reference input in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs. The circuit also has processing means for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified is not symmetrical.
摘要翻译： 电路具有连接到差分放大器的输出的双半波整流器，以便产生取决于放大器的输出信号的半波幅度的两个量。 每个具有输入的两个比较器连接到整流器的输出和参考输入，以便当相应的半波的幅度大于施加到参考输入的电平时产生相应的输出信号。 电路还具有用于根据两个比较器的输出信号的持续时间产生用于调节放大器的增益的信号的处理装置。 当待放大的信号不对称时，可以有利地使用该电路。
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