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公开(公告)号：US5654675A
公开(公告)日：1997-08-05
申请号：US611831
申请日：1996-03-06
CPC分类号： H03L7/0891 , H03L7/099 , H03L7/107 , H03L2207/04 , H03L7/0995
摘要： A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.
摘要翻译： 具有改进的抖动特性的完全集成的锁相环（PLL）使用相同的数/模转换器（DAC），其通常用于控制低通环路滤波器的时间常数，以控制连接在输出端 压控振荡器和地的电压 - 电流转换输入级。 电容在循环传递函数中引入了第三极点。 以这种方式，传递函数的零和第三极之间的频域分离保持不变; 因此，阻尼因子保持恒定，同时PLL的ω0变化。
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公开(公告)号：US5714903A
公开(公告)日：1998-02-03
申请号：US575872
申请日：1995-12-21
CPC分类号： G06G7/163
摘要： An analog multiplier includes at least a differential output stage formed by a pair of emitter-coupled bipolar transistors. Each transistor of the pair of emitter-coupled bipolar transistors is driven by a predistortion stage having a reciprocal of a hyperbolic tangent transfer function that is attributable to the base currents of the bipolar transistors used in the predistortion stage. The error in the output signal produced by the analog multiplier is compensated by generating replicas of the base currents of the bipolar transistors of the differential output stage and forcing those replica currents on the output node of a respective predistortion stage. Various embodiments that consume different amounts of power are described.
摘要翻译： 模拟乘法器至少包括由一对发射极耦合双极晶体管形成的差分输出级。 一对发射极耦合双极晶体管中的每个晶体管由具有双曲正切传递函数的倒数的预失真级驱动，该双曲正切转移函数归因于在预失真级中使用的双极型晶体管的基极电流。 由模拟乘法器产生的输出信号中的误差通过产生差分输出级的双极晶体管的基极电流的副本并且迫使在相应的预失真级的输出节点上的那些复制电流来补偿。 描述消耗不同功率量的各种实施例。
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公开(公告)号：US06414810B1
公开(公告)日：2002-07-02
申请号：US09301192
申请日：1999-04-28
IPC分类号： G11B5035
CPC分类号： G11B20/10046 , G11B2220/2516
摘要： A method of equalizing a read channel of a mass magnetic memory device comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order in a range from 6 to 8 and a boost is implemented by introducing two real and opposed zeroes in the transfer function of the filter without altering the group delay.
摘要翻译： 均衡质量磁存储器件的读通道的方法包括衰减源自电磁读取换能器的模拟信号的频谱的低频，而不会增加频谱的高频谐波分量。 模拟输入信号的频谱的低频通过6至8范围内的阶数的低通滤波器衰减，并且通过在滤波器的传递函数中引入两个实数和相对的零来实现升压，而不改变 群延迟
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4.发明授权
公开(公告)号：US6140867A
公开(公告)日：2000-10-31
申请号：US312003
申请日：1999-05-14
CPC分类号： H03F3/3001 , H03H11/0472
摘要： Embodiments of the invention provide a transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor across which a constant voltage is input. The transconductor is connected to a digital-to-analog converter (DAC) to set a reference current. A feedback loop is provided between an output of the transconductor and an input. In particular, the circuit further comprises a means for mirroring the reference current set by the DAC both to the feedback loop and to at least one cell of a cascade-connected filter.
摘要翻译： 本发明的实施例提供跨导控制电路，特别是对于连续时间滤波器，包括跨导体，跨导体输入恒定电压。 跨导体连接到数模转换器（DAC）以设置参考电流。 在跨导体的输出和输入之间提供反馈回路。 特别地，电路还包括用于将DAC设置的参考电流镜像到反馈回路和级联连接的滤波器的至少一个单元的装置。
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公开(公告)号：US06466097B1
公开(公告)日：2002-10-15
申请号：US09421643
申请日：1999-10-20
IPC分类号： H03L706
CPC分类号： H03L7/0893 , H03L7/0896
摘要： A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current. In a preferred embodiment, the circuit breaking switches are controlled by phase error signals from the phase comparator. A method for controlling a charge pump circuit in a phase locked loop is also provided.
摘要翻译： 提供了一个锁相环，其包括相位比较器，电荷泵电路，环路滤波器和压控振荡器。 电荷泵电路包括两个对称分支，反馈路径和断路开关。 每个对称分支具有恒定电流发生器和脉冲电流发生器，环路滤波器的一个端子连接到一个对称分支，并且环路滤波器的另一个端子连接到另一个对称分支。 反馈路径基于环路滤波器的端子处的电压来控制恒定电流发生器，并且每个断路开关耦合脉冲电流发生器中的一个和环路滤波器的相应端子。 脉冲电流发生器通过第一电流的占空比来提供其振幅与由恒定电流发生器提供的第二电流的振幅成比例的第一电流。 在优选实施例中，断路开关由来自相位比较器的相位误差信号控制。 还提供了一种用于控制锁相环中的电荷泵电路的方法。
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6.发明授权Analog-to-digital flash converter for generating a thermometric digital code 有权用于产生温度数字代码的模拟 - 数字闪存转换器公开(公告)号：US06346905B1
公开(公告)日：2002-02-12
申请号：US09447065
申请日：1999-11-22
IPC分类号： H03M1300
CPC分类号： H03M1/0809 , H03M1/365
摘要： A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.
摘要翻译： 闪存模数转换器包括具有差分输出的一组比较器，产生测温代码和一组三输入逻辑或非门。 通过提供包括多个分压器的无源接口，每个连接在相应比较器的非反相输出端和该组的较高阶比较器的反相输出端之间，该转换器具有增强的抗噪声能力和减小的不精确性。 该组的对应逻辑或非门具有耦合到相应比较器的反相输出的第一输入，耦合到高阶比较器的非反相输出的第二输入和耦合到分压器的中间节点的第三输入。
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7.发明授权Reduced current quadratic digital/analog converter with improved settling-time 失效减少电流二次数字/模拟转换器，提高了建立时间
公开(公告)号：US5748128A
公开(公告)日：1998-05-05
申请号：US645457
申请日：1996-05-13
摘要： A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.
摘要翻译： 由串联连接的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合 DAC2）对应于R-2R型电阻网络的LSB级。 有利地，从“电流路径”消除高阻抗节点，特别是第二线性转换器的输入节点，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。 二次转换器的独特结构也为电路的显着简化提供了依据。
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8.发明授权Circuit and method for determining the position of a read head for a magnetic disk drive device 有权用于确定用于磁盘驱动装置的读取头的位置的电路和方法公开(公告)号：US06204990B1
公开(公告)日：2001-03-20
申请号：US09412080
申请日：1999-10-04
IPC分类号： G11B5596
CPC分类号： G11B5/59688 , G11B5/5534 , G11B5/59605
摘要： A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the center of a recorded track. The servo-demodulator comprises a peak detector for successively and individually sampling the amplitude of each of a plurality of peaks of the pair of alternating signals, and a capacitor periodically connected to the output of the peak detector by a control logic for deriving a weighted average of the various successively sampled amplitudes. In this manner, the control logic obtains an averaged measure of amplitude with high immunity to noise.
摘要翻译： 一种用于由磁盘读取头产生的一对交替信号的伺服解调器，并且指示读取头相对于记录轨道的中心的位置。 伺服解调器包括峰值检测器，用于连续和单独地采样该对交变信号的多个峰值中的每一个的振幅;以及电容器，通过用于导出加权平均值的控制逻辑周期性地连接到峰值检测器的输出端 的各种连续采样幅度。 以这种方式，控制逻辑获得具有高抗噪声能力的幅度的平均测量值。
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公开(公告)号：US5914642A
公开(公告)日：1999-06-22
申请号：US777472
申请日：1996-12-30
CPC分类号： H03K3/2821
摘要： A current-controlled multivibrator having increased accuracy independent of variations in process and temperature. The oscillator employs a bandgap voltage in combination with a current generator to ensure operational stability despite temperature and process variations.
摘要翻译： 电流控制的多谐振荡器具有独立于工艺和温度变化的精度增加。 振荡器采用与电流发生器组合的带隙电压，以确保尽管温度和工艺变化，操作稳定性。
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公开(公告)号：US06654192B1
公开(公告)日：2003-11-25
申请号：US09294642
申请日：1999-04-19
IPC分类号： G11B509
CPC分类号： G01R19/22
摘要： A full-wave rectifier for monitoring the amplitude of a differential analog signal includes a differential Track&Hold stage controlled by a first differential logic timing signal tracking the differential analog input signal during a tracking phase that corresponds to a high logic stage of the first differential timing signal. This produces a differential output signal that is a replica of the input signal and the signal is stored during a successive storing phase that corresponds to a low logic state of the first differential timing signal. A first differential output amplifier includes inputs coupled to the output of the Track&Hold stage. A differential bistable circuit, controlled by a second differential logic timing signal, includes inputs coupled to the differential outputs of the first amplifier and produces a third differential logic control signal. A second multiplexed amplifier, controlled by the third differential control signal, includes inputs coupled to the output of the Track&Hold stage and produces a differential analog signal having an amplitude function corresponding to the amplitude of the differential input signal. A timing circuit receives at an input a differential logic synchronizing signal and generates the first differential timing signal of the Track&Hold stage and the second differential timing signal of the bistable circuit.
摘要翻译： 用于监视差分模拟信号的幅度的全波整流器包括差分跟踪和保持级，该差分跟踪保持级由跟踪第一差分定时信号的高逻辑级的跟踪阶段期间的差分模拟输入信号的第一差分逻辑定时信号控制 。 这产生作为输入信号的副本的差分输出信号，并且在对应于第一差分定时信号的低逻辑状态的连续存储阶段期间存储信号。 第一差分输出放大器包括耦合到跟踪和保持级的输出的输入。 由第二差分逻辑定时信号控制的差分双稳态电路包括耦合到第一放大器的差分输出并输出第三差分逻辑控制信号的输入。 由第三差分控制信号控制的第二多路复用放大器包括耦合到跟踪和保持级的输出的输入，并且产生具有对应于差分输入信号的幅度的幅度函数的差分模拟信号。 定时电路在输入端接收差分逻辑同步信号，并产生跟踪和保持级的第一差分定时信号和双稳态电路的第二差分定时信号。
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