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1.发明授权
公开(公告)号：US5805022A
公开(公告)日：1998-09-08
申请号：US713715
申请日：1996-09-13
CPC分类号： H03G3/3026 , G11B5/02 , H03G1/0088
摘要： A circuit having a double half-wave rectifier connected to the outputs of a differential amplifier in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier. Two comparators each having an input are connected to an output of the rectifier and a reference input in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs. The circuit also has processing means for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified is not symmetrical.
摘要翻译： 电路具有连接到差分放大器的输出的双半波整流器，以便产生取决于放大器的输出信号的半波幅度的两个量。 每个具有输入的两个比较器连接到整流器的输出和参考输入，以便当相应的半波的幅度大于施加到参考输入的电平时产生相应的输出信号。 电路还具有用于根据两个比较器的输出信号的持续时间产生用于调节放大器的增益的信号的处理装置。 当待放大的信号不对称时，可以有利地使用该电路。
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2.发明授权Reduced current quadratic digital/analog converter with improved settling-time 失效减少电流二次数字/模拟转换器，提高了建立时间
公开(公告)号：US5748128A
公开(公告)日：1998-05-05
申请号：US645457
申请日：1996-05-13
摘要： A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.
摘要翻译： 由串联连接的一对线性转换器组成的数字/模拟二次转换器（DACQ）具有第一转换器（DAC1）的输出节点与第二转换器的R-2R型电阻网络的节点的直接耦合 DAC2）对应于R-2R型电阻网络的LSB级。 有利地，从“电流路径”消除高阻抗节点，特别是第二线性转换器的输入节点，从而显着地减少了高阻抗节点（具有与其相关的本质上大的寄生电容）的较长建立时间的问题。 二次转换器的独特结构也为电路的显着简化提供了依据。
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公开(公告)号：US5805015A
公开(公告)日：1998-09-08
申请号：US629320
申请日：1996-04-08
摘要： A current generator stage for integrated analog circuits includes a current source connected between a supply voltage and a ground terminal. A current mirror is operationally connected to the current source to generate an output current. A bias circuit is operationally connected to the current source to perform switching of the current source from a first operating mode to a second operating mode. The bias circuit includes an energy storage circuit which, in a first circuit configuration, supplies to the current source a first predetermined voltage when the current source is in the first operating mode. The energy storage circuit in a second circuit configuration is a combination of first and second reactances to supply to the current source a second predetermined voltage when the current source is in the second operating mode.
摘要翻译： 用于集成模拟电路的电流发生器级包括连接在电源电压和接地端子之间的电流源。 电流镜可操作地连接到电流源以产生输出电流。 偏置电路可操作地连接到电流源，以将电流源从第一操作模式切换到第二操作模式。 偏置电路包括能量存储电路，其在第一电路配置中，当电流源处于第一操作模式时，向电流源提供第一预定电压。 第二电路配置中的能量存储电路是第一和第二电抗的组合，以在电流源处于第二操作模式时向电流源提供第二预定电压。
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公开(公告)号：US5736880A
公开(公告)日：1998-04-07
申请号：US576882
申请日：1995-12-21
CPC分类号： H03L7/0896
摘要： A differential charge pump circuit employing a lowpass filter network which is chargeable and dischargeable by switchingly controlled current generators. The differential charge pump employs two identical current generators for injecting the same current I in a substantially continuous manner, on the two significant nodes of the lowpass filter. The differential charge pump also employs two pairs of identical, switchingly controlled current generators connected to the two significant nodes, respectively, each capable of pulling a current I. The two generators forming each of the two pairs of switchingly controlled current generators are controlled by one of a pair of control signals (UP, DOWN) and by the inverted signal of the other of the pair of control signals, respectively. All four switchingly controlled generators may be of the same type (N-type), thus ensuring high speed and precision. The two identical (P-type) current generators employed for continuously injecting the same current I on the two nodes of the lowpass filter may be controlled through a common mode feedback loop for enhanced precision.
摘要翻译： 采用低通滤波器网络的差分电荷泵电路，该低通滤波器网络可由切换控制的电流发生器进行充电和放电。 差分电荷泵采用两个相同的电流发生器，以基本上连续的方式在低通滤波器的两个重要节点上注入相同的电流I。 差分电荷泵还采用两对相同的交换控制电流发生器，分别连接到两个有效节点，每个有效节点能够拉电流I.形成两对开关控制电流发生器中的每一对的两个发电机由一个 一对控制信号（UP，DOWN）和另一对控制信号的反相信号。 所有四个交流控制发电机可以是相同类型（N型），从而确保高速度和精度。 用于在低通滤波器的两个节点上连续注入相同电流I的两个相同（P型）电流发生器可以通过共模反馈回路来控制，以提高精度。
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公开(公告)号：US6002542A
公开(公告)日：1999-12-14
申请号：US904599
申请日：1997-08-01
CPC分类号： G11B5/59688 , G11B5/59605 , G11B5/5534
摘要： A servo-demodulator for a pair of alternating signals generated by a magnetic disc read head and indicative of the position of the read head in relation to the center of a recorded track. The servo-demodulator comprises a peak detector for successively and individually sampling the amplitude of each of a plurality of peaks of the pair of alternating signals, and a capacitor periodically connected to the output of the peak detector by a control logic for deriving a weighted average of the various successively sampled amplitudes. In this manner, the control logic obtains an averaged measure of amplitude with high immunity to noise.
摘要翻译： 一种用于由磁盘读取头产生的一对交替信号的伺服解调器，并且指示读取头相对于记录轨道的中心的位置。 伺服解调器包括峰值检测器，用于连续和单独地采样该对交变信号的多个峰值中的每一个的振幅;以及电容器，通过用于导出加权平均值的控制逻辑周期性地连接到峰值检测器的输出端 的各种连续采样幅度。 以这种方式，控制逻辑获得具有高抗噪声能力的幅度的平均测量值。
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公开(公告)号：US06466097B1
公开(公告)日：2002-10-15
申请号：US09421643
申请日：1999-10-20
IPC分类号： H03L706
CPC分类号： H03L7/0893 , H03L7/0896
摘要： A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current. In a preferred embodiment, the circuit breaking switches are controlled by phase error signals from the phase comparator. A method for controlling a charge pump circuit in a phase locked loop is also provided.
摘要翻译： 提供了一个锁相环，其包括相位比较器，电荷泵电路，环路滤波器和压控振荡器。 电荷泵电路包括两个对称分支，反馈路径和断路开关。 每个对称分支具有恒定电流发生器和脉冲电流发生器，环路滤波器的一个端子连接到一个对称分支，并且环路滤波器的另一个端子连接到另一个对称分支。 反馈路径基于环路滤波器的端子处的电压来控制恒定电流发生器，并且每个断路开关耦合脉冲电流发生器中的一个和环路滤波器的相应端子。 脉冲电流发生器通过第一电流的占空比来提供其振幅与由恒定电流发生器提供的第二电流的振幅成比例的第一电流。 在优选实施例中，断路开关由来自相位比较器的相位误差信号控制。 还提供了一种用于控制锁相环中的电荷泵电路的方法。
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7.发明授权Analog-to-digital flash converter for generating a thermometric digital code 有权用于产生温度数字代码的模拟 - 数字闪存转换器公开(公告)号：US06346905B1
公开(公告)日：2002-02-12
申请号：US09447065
申请日：1999-11-22
IPC分类号： H03M1300
CPC分类号： H03M1/0809 , H03M1/365
摘要： A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.
摘要翻译： 闪存模数转换器包括具有差分输出的一组比较器，产生测温代码和一组三输入逻辑或非门。 通过提供包括多个分压器的无源接口，每个连接在相应比较器的非反相输出端和该组的较高阶比较器的反相输出端之间，该转换器具有增强的抗噪声能力和减小的不精确性。 该组的对应逻辑或非门具有耦合到相应比较器的反相输出的第一输入，耦合到高阶比较器的非反相输出的第二输入和耦合到分压器的中间节点的第三输入。
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公开(公告)号：US5914642A
公开(公告)日：1999-06-22
申请号：US777472
申请日：1996-12-30
CPC分类号： H03K3/2821
摘要： A current-controlled multivibrator having increased accuracy independent of variations in process and temperature. The oscillator employs a bandgap voltage in combination with a current generator to ensure operational stability despite temperature and process variations.
摘要翻译： 电流控制的多谐振荡器具有独立于工艺和温度变化的精度增加。 振荡器采用与电流发生器组合的带隙电压，以确保尽管温度和工艺变化，操作稳定性。
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公开(公告)号：US5714903A
公开(公告)日：1998-02-03
申请号：US575872
申请日：1995-12-21
CPC分类号： G06G7/163
摘要： An analog multiplier includes at least a differential output stage formed by a pair of emitter-coupled bipolar transistors. Each transistor of the pair of emitter-coupled bipolar transistors is driven by a predistortion stage having a reciprocal of a hyperbolic tangent transfer function that is attributable to the base currents of the bipolar transistors used in the predistortion stage. The error in the output signal produced by the analog multiplier is compensated by generating replicas of the base currents of the bipolar transistors of the differential output stage and forcing those replica currents on the output node of a respective predistortion stage. Various embodiments that consume different amounts of power are described.
摘要翻译： 模拟乘法器至少包括由一对发射极耦合双极晶体管形成的差分输出级。 一对发射极耦合双极晶体管中的每个晶体管由具有双曲正切传递函数的倒数的预失真级驱动，该双曲正切转移函数归因于在预失真级中使用的双极型晶体管的基极电流。 由模拟乘法器产生的输出信号中的误差通过产生差分输出级的双极晶体管的基极电流的副本并且迫使在相应的预失真级的输出节点上的那些复制电流来补偿。 描述消耗不同功率量的各种实施例。
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10.发明授权Method and device for delaying selected transitions in a digital data stream 有权用于延迟数字数据流中所选择的转换的方法和装置公开(公告)号：US06208184B1
公开(公告)日：2001-03-27
申请号：US09451051
申请日：1999-11-30
IPC分类号： H03L700
CPC分类号： G11B20/10009 , G11B5/012 , G11B5/09
摘要： A method and circuit are provided for delaying a transition in a digital data stream fed to a write head of a mass storage device by a certain time interval when the transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbol nonlinear interference effects suffered when reading the stored data. The method includes feeding digital data stream to be stored and a clock signal to a first circuit and outputting a pair of digital streams from the first circuit. The first stream assumes a first logic value every time a transition of the input stream occurs during a clock phase not successive to a clock phase during which a transition of the input stream has occurred. The second stream assumes the first logic value every time a transition of the input stream occurs during a clock phase following a clock phase during which a transition has taken place in the input stream. The method also includes feeding the two digital streams and the clock signal to the inputs of a second circuit and outputting the digital data stream from the second circuit directed to the write head. The transitions immediately following a preceding transition are delayed by the pre-established time interval, by sampling the two digital streams with a pair of flip-flops, each of which is respectively timed by clock signals respectively delayed by a certain different time interval.
摘要翻译： 提供了一种方法和电路，用于当在发生先前转换的时钟阶段发生转换时，将馈送到大容量存储设备的写入头的数字数据流中的转变延迟一定的时间间隔，以便 读取存储的数据时遇到的补偿前符号非线性干扰效应。 该方法包括将待存储的数字数据流和时钟信号馈送到第一电路，并从第一电路输出一对数字流。 每当在不连续输入流的转换的时钟相位的时钟相位期间，输入流的转变发生时，第一流假设第一逻辑值。 每当在输入流中发生转换的时钟相位之后的时钟相位期间，输入流的转变发生时，第二流假设第一逻辑值。 该方法还包括将两个数字流和时钟信号馈送到第二电路的输入，并从指向写入头的第二电路输出数字数据流。 通过用一对触发器对两个数字流进行采样来分别由分别延迟了某个不同的时间间隔的时钟信号定时，通过先前转换之后的转换被延迟预先建立的时间间隔。
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