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公开(公告)号:US20220165722A1
公开(公告)日:2022-05-26
申请号:US17381985
申请日:2021-07-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Sang Cheon PARK , Dae-Woo Kim , Taehun Kim , Hyuekjae Lee
IPC: H01L25/18 , H01L23/31 , H01L23/498 , H01L23/48
Abstract: A semiconductor package includes a redistribution substrate, a first memory chip provided on the redistribution substrate, the first memory chip comprising a first base layer, a first circuit layer provided on a top surface of the first base layer, and a first via penetrating the first base layer and connected to the first circuit layer and the redistribution substrate, a logic chip provided on the first memory chip, and a first molding layer surrounding the first memory chip. An outer side surface of the first molding layer is coplanar with a side surface of the logic chip. At an interface of the logic chip and the first memory chip, a first chip pad provided in the first circuit layer of the first memory chip and a second chip pad of the logic chip are formed of the same material and constitute one body.
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公开(公告)号:US11244927B2
公开(公告)日:2022-02-08
申请号:US16833761
申请日:2020-03-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyuekjae Lee , Jihoon Kim , Jihwan Suh , Soyoun Lee , Jiseok Hong , Taehun Kim , Jihwan Hwang
IPC: H01L23/16 , H01L25/065 , H01L23/00 , H01L23/538 , H01L23/31
Abstract: Provided is a semiconductor package including a semiconductor stack including a first lower chip, a second lower chip, a gap filler disposed between the first lower chip and the second lower chip, and a first upper chip disposed on an upper surface of the first lower chip, an upper surface of the second lower chip, and an upper surface of the gap filler, the first lower chip includes first upper surface pads and a first upper surface dielectric layer, the second lower chip includes second upper surface pads and a second upper surface dielectric layer, the first upper chip includes lower surface pads and a lower surface dielectric layer, and an area of an upper surface of each of the second upper surface pads is greater than an area of a lower surface of each of the lower surface pads.
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公开(公告)号:US11158594B2
公开(公告)日:2021-10-26
申请号:US17007223
申请日:2020-08-31
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jiseok Hong , Hyuekjae Lee , Jongpa Hong , Jihwan Hwang , Taehun Kim
IPC: H01L23/00 , H01L25/065 , H01L23/48
Abstract: A semiconductor package includes a first semiconductor chip having a through-electrode and an upper connection pad on an upper surface of the first semiconductor chip that is connected to the through-electrode; a second semiconductor chip stacked on the first semiconductor chip, and having a lower connection pad on a lower surface of the second semiconductor chip; a non-conductive film between the first semiconductor chip and the second semiconductor chip, with the non-conductive film including voids having an average diameter of 1 μm to 100 μm, the voids having a volume fraction of 0.1 to 5 vol %; and a connection conductor that penetrates the non-conductive film and connects the upper connection pad and the lower connection pad.
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公开(公告)号:US20210217929A1
公开(公告)日:2021-07-15
申请号:US16940879
申请日:2020-07-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taehun Kim , Dongmyung Shin , Minho Kim , Minwook Choi
Abstract: A light emitting device may include a light emitting structure, a transparent electrode, a first insulation layer, a first electrode, a second insulation layer and a second electrode. The light emitting structure may include a first semiconductor layer, an activation layer and a second semiconductor layer sequentially stacked. The transparent electrode may be formed on an upper surface of the second semiconductor layer. The transparent electrode may have at least one opening. The first insulation layer may be formed on an upper surface of the transparent electrode to fill the at least one opening. The first electrode may be formed on an upper surface of the first insulation layer. The first electrode may include a contact extending through the first insulation layer and connected with the transparent electrode. The second insulation layer may be formed on an upper surface of the first electrode. The second electrode may be formed on an upper surface of the second insulation layer. The second electrode may be electrically connected with the first semiconductor layer.
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公开(公告)号:US10199551B2
公开(公告)日:2019-02-05
申请号:US15636084
申请日:2017-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taehun Kim , Jae-Yoon Kim , Youngkyu Sung , Gamham Yong , Dongyeoul Lee , Suyeol Lee
Abstract: A semiconductor light-emitting device includes a light-emitting structure including a first semiconductor layer, an active layer and a second semiconductor layer sequentially stacked. A connection electrode is positioned above the light-emitting structure. The connection electrode includes a connection metal layer electrically connected to at least one of the first and second semiconductor layers. A UBM pattern is on the connection electrode. A connection terminal is on the UBM pattern. The connection metal layer includes a first metal element. A heat conductivity of the first metal element is higher than that of gold (Au). The connection terminal includes a second metal element. A first reactivity of the first metal element with the second metal element is lower than a second reactivity of gold (Au) with the second metal element.
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公开(公告)号:US10032706B2
公开(公告)日:2018-07-24
申请号:US15236868
申请日:2016-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: JinGyu Kim , Taehun Kim , JiSun Hong , Byungmoon Bae , Se-Ho You
IPC: H01L23/498 , H01L23/00 , H01L23/60 , H01L23/29
CPC classification number: H01L23/49838 , H01L23/293 , H01L23/49816 , H01L23/562 , H01L23/60 , H01L24/13 , H01L24/16 , H01L2224/13109 , H01L2224/13111 , H01L2224/13113 , H01L2224/1312 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16237 , H01L2924/1431 , H01L2924/1434 , H01L2924/15311 , H01L2924/3511
Abstract: A package substrate includes a substrate including a circuit region, a dummy region surrounding the circuit region, and a lower circuit pattern at the dummy region, the circuit region including unit regions arranged in a matrix shape, and solders on the lower circuit pattern, at least one of the solders electrically connected to the lower circuit pattern.
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公开(公告)号:USD758980S1
公开(公告)日:2016-06-14
申请号:US29494038
申请日:2014-06-17
Applicant: Samsung Electronics Co., Ltd.
Designer: Taehun Kim , Chaejoo Son
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公开(公告)号:USD747300S1
公开(公告)日:2016-01-12
申请号:US29518470
申请日:2015-02-24
Applicant: Samsung Electronics Co., Ltd.
Designer: Hee-Bong Kim , Taehun Kim , Jae Neung Lee
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公开(公告)号:USD746799S1
公开(公告)日:2016-01-05
申请号:US29518479
申请日:2015-02-24
Applicant: Samsung Electronics Co., Ltd.
Designer: Hee-Bong Kim , Taehun Kim , Jae Neung Lee
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公开(公告)号:USD725087S1
公开(公告)日:2015-03-24
申请号:US29493433
申请日:2014-06-10
Applicant: Samsung Electronics Co., Ltd.
Designer: Taehun Kim , Chaejoo Son
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