公开(公告)号：US11444016B2

公开(公告)日：2022-09-13

申请号：US16886695

申请日：2020-05-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L27/115 ,  H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L49/02 ,  H01L27/11582

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad and the ground I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the signal lines and/or above device capacitors on the top surface of the substrate.

公开(公告)号：US11270963B2

公开(公告)日：2022-03-08

申请号：US16742213

申请日：2020-01-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chen Wu ,  Peter Rabkin ,  Masaaki Higashitani

IPC: H01L23/00 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11526 ,  H01L25/00

Abstract: A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

公开(公告)号：US11031088B2

公开(公告)日：2021-06-08

申请号：US16909830

申请日：2020-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/4074 ,  G11C11/56

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

公开(公告)号：US10903222B2

公开(公告)日：2021-01-26

申请号：US16408722

申请日：2019-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Kiyohiko Sakakibara ,  Masaaki Higashitani ,  Masanori Tsutsumi ,  Zhixin Cui

IPC: H01L27/1157 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L23/535 ,  H01L21/285 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: A three-dimensional memory device includes source-level material layers located over a substrate and including a lower semiconductor layer, a source contact layer, and an upper semiconductor layer. The lower semiconductor layer includes a first boron-doped semiconductor material, the upper semiconductor layer includes carbon doped second boron-doped semiconductor material, and the source contact layer includes a boron-doped semiconductor material. An alternating stack of insulating layers and electrically conductive layers is located over the source-level material layers. Memory stack structures vertically extend through the alternating stack, the upper semiconductor layer, and the source contact layer. Each of the memory stack structures includes a respective memory film and a respective vertical semiconductor channel that contacts the source contact layer. Carbon atoms in the upper semiconductor layer and optionally the lower semiconductor layer suppress diffusion of boron atoms into the vertical semiconductor channel.

公开(公告)号：US10789992B2

公开(公告)日：2020-09-29

申请号：US16168168

申请日：2018-10-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Luisa Lin ,  Mohan Dunga ,  Venkatesh P. Ramachandra ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C11/24 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573 ,  G11C16/08 ,  G11C5/10 ,  G11C16/28 ,  G11C16/24 ,  H01L27/11578

Abstract: A non-volatile storage apparatus comprises a non-volatile memory structure and a plurality of I/O pads in communication with the non-volatile memory structure. The I/O pads include a power I/O pad, a ground I/O pad and data/control I/O pads. The non-volatile storage apparatus further comprises one or more capacitors connected to the power I/O pad. The one or more capacitors are positioned in one or more metal interconnect layers below the I/O pads.

公开(公告)号：US10726926B2

公开(公告)日：2020-07-28

申请号：US16248000

申请日：2019-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C7/04 ,  G11C16/04 ,  G11C11/4074 ,  G11C11/56

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

公开(公告)号：US20200105349A1

公开(公告)日：2020-04-02

申请号：US16248000

申请日：2019-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dae Wung Kang ,  Peter Rabkin ,  Masaaki Higashitani

IPC: G11C16/26 ,  G11C7/04 ,  G11C11/56 ,  G11C11/4074 ,  G11C16/04

Abstract: Methods and systems for improving the reliability of data stored within a semiconductor memory over a wide range of operating temperatures are described. The amount of shifting in the threshold voltages of memory cell transistors over temperature may depend on the location of the memory cell transistors within a NAND string. To compensate for these variations, the threshold voltages of memory cell transistors in the middle of the NAND string or associated with a range of word lines between the ends of the NAND string may be adjusted by increasing the word line voltages biasing memory cell transistors on the drain-side of the selected word line when the read temperature is greater than a first threshold temperature and/or decreasing the word line voltages biasing memory cell transistors on the source-side of the selected word line when the read temperature is less than a second threshold temperature.

公开(公告)号：US09818801B1

公开(公告)日：2017-11-14

申请号：US15293971

申请日：2016-10-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Perumal Ratnam ,  Christopher J. Petti ,  Masaaki Higashitani

IPC: H01L27/115 ,  H01L45/00 ,  H01L29/778 ,  H01L27/24 ,  H01L23/528 ,  H01L29/205 ,  H01L29/12 ,  H01L29/66 ,  H01L27/11582 ,  H01L29/78

CPC classification number: H01L27/2481 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/2409 ,  H01L29/122 ,  H01L29/205 ,  H01L29/66462 ,  H01L29/778 ,  H01L29/7833 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608

Abstract: A three-dimensional resistive memory device includes an alternating stack of electrically conductive layers and insulating layers. Resistive memory elements are provided between the electrically conductive layers and a semiconductor local bit line. The semiconductor local bit line includes a heterostructure of an inner semiconductor material layer having an inner-material band gap and an outer semiconductor material layer having an outer-material band gap that is narrower than the inner-material band. A gate dielectric is located between a gate electrode and the inner semiconductor material layer.

公开(公告)号：US12245425B2

公开(公告)日：2025-03-04

申请号：US17673137

申请日：2022-02-16

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Peter Rabkin ,  Masaaki Higashitani

IPC: H10B41/27 ,  H01L29/15 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device containing a plurality of levels of memory elements includes a memory film containing a layer stack that includes a resonant tunneling barrier stack, a semiconductor barrier layer, and a memory material layer located between the resonant tunneling barrier stack and the semiconductor barrier layer, a semiconductor channel, and a control gate electrode.

公开(公告)号：US12217965B2

公开(公告)日：2025-02-04

申请号：US17573429

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Yujin Terasawa ,  Naoki Takeguchi ,  Kensuke Yamaguchi ,  Masaaki Higashitani

IPC: H01L21/285 ,  C23C16/14 ,  C23C16/455 ,  H01L21/768 ,  H10B41/27 ,  H10B43/27 ,  H10B51/20 ,  H10B63/00

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.