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    Method for manufacturing SOI substrate and semiconductor device
    21.
    发明授权
    Method for manufacturing SOI substrate and semiconductor device 有权
    制造SOI衬底和半导体器件的方法

    公开(公告)号：US08629031B2

    公开(公告)日：2014-01-14

    申请号：US13759264

    申请日：2013-02-05

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Yasuhiro Jinbo ,  Hironobu Shoji ,  Hideto Ohnuma ,  Shunpei Yamazaki

    IPC: H01L21/331 ,  H01L21/8222

    CPC classification number: H01L21/84 ,  H01L21/26506 ,  H01L21/76254

    Abstract: It is an object of the present invention to provide a method for manufacturing an SOI substrate having an SOI layer that can be used in practical applications with high yield even when a flexible substrate such as a glass substrate or a plastic substrate is used. Further, it is another object of the present invention to provide a method for manufacturing a thin semiconductor device using such an SOI substrate with high yield. When a single-crystal semiconductor substrate is bonded to a flexible substrate having an insulating surface and the single-crystal semiconductor substrate is separated to manufacture an SOI substrate, one or both of bonding surfaces are activated, and then the flexible substrate having an insulating surface and the single-crystal semiconductor substrate are attached to each other.

    Abstract translation: 本发明的目的是提供一种制造具有SOI层的SOI衬底的方法，该SOI衬底即使在使用诸如玻璃衬底或塑料衬底的柔性衬底时，也可以在实际应用中以高产率使用。 此外，本发明的另一个目的是提供一种以高产率制造使用这种SOI衬底的薄半导体器件的方法。 当将单晶半导体衬底接合到具有绝缘表面的柔性衬底并且分离单晶半导体衬底以制造SOI衬底时，一个或两个键合表面被激活，然后柔性衬底具有绝缘表面 并且单晶半导体衬底彼此附接。

    Semiconductor device and manufacturing method thereof
    26.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US09224792B2

    公开(公告)日：2015-12-29

    申请号：US14496168

    申请日：2014-09-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hideaki Kuwabara ,  Hideto Ohnuma

    IPC: H01L33/06 ,  H01L27/32 ,  H01L33/36 ,  H01L51/00

    CPC classification number: H01L51/56 ,  H01L27/3241 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L33/36 ,  H01L51/0011 ,  H01L51/52 ,  H01L2251/5338

    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

    Abstract translation: 由于与清晰度的改善相关联的像素区域的小型化以及与面积的增加相关联的基板尺寸的增加，由于在蒸发时使用的掩模的精度，弯曲等的缺陷已经变成 问题 通过使用光掩模或掩模版形成在显示区域和像素电极层附近的像素电极（也称为第一电极）上具有不同厚度的部分，而不增加步骤数 具有由衍射光栅图案或半透射膜构成的具有光强度降低功能的辅助图案。

    Semiconductor Device and Manufacturing Method Thereof
    27.
    发明申请
    Semiconductor Device and Manufacturing Method Thereof 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150069367A1

    公开(公告)日：2015-03-12

    申请号：US14496168

    申请日：2014-09-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd

    Inventor： Hideaki Kuwabara ,  Hideto Ohnuma

    IPC: H01L27/32

    CPC classification number: H01L51/56 ,  H01L27/3241 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L33/36 ,  H01L51/0011 ,  H01L51/52 ,  H01L2251/5338

    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

    Abstract translation: 由于与清晰度的改善相关联的像素区域的小型化以及与面积的增加相关联的基板尺寸的增加，由于在蒸发时使用的掩模的精度，弯曲等的缺陷已经变成 问题 通过使用光掩模或掩模版形成在显示区域和像素电极层附近的像素电极（也称为第一电极）上具有不同厚度的部分，而不增加步骤数 具有由衍射光栅图案或半透射膜构成的具有光强度降低功能的辅助图案。

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    28.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
    半导体器件及其制造方法

    公开(公告)号：US20140332867A1

    公开(公告)日：2014-11-13

    申请号：US14340717

    申请日：2014-07-25

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Masayuki Sakakura ,  Hideto Ohnuma ,  Hideaki Kuwabara

    IPC: H01L27/12 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H01L27/1244 ,  H01L21/32139 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76879 ,  H01L21/76886 ,  H01L23/528 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1274 ,  H01L27/1288 ,  H01L27/3276 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: It is an object of the present invention to provide a method for preventing a breaking and poor contact, without increasing the number of steps, thereby forming an integrated circuit with high driving performance and reliability. The present invention applies a photo mask or a reticle each of which is provided with a diffraction grating pattern or with an auxiliary pattern formed of a semi-translucent film having a light intensity reducing function to a photolithography step for forming wires in an overlapping portion of wires. And a conductive film to serve as a lower wire of a two-layer structure is formed, and then, a resist pattern is formed so that a first layer of the lower wire and a second layer narrower than the first layer are formed for relieving a steep step.

    Abstract translation: 本发明的目的是提供一种防止接触不良而不增加步数的方法，从而形成具有高驱动性能和可靠性的集成电路。 本发明应用了一种光掩模或掩模版，每个光掩模或光掩模具有衍射光栅图案或由具有光强度降低功能的半透明膜形成的辅助图案，用于在光刻步骤中形成导线的重叠部分 电线 并且形成用作二层结构的下导线的导电膜，然后形成抗蚀剂图案，使得形成下线的第一层和比第一层窄的第二层以缓解 陡峭的一步。

    SOI substrate and manufacturing method thereof
    29.
    发明授权
    SOI substrate and manufacturing method thereof 有权
    SOI衬底及其制造方法

    公开(公告)号：US08884371B2

    公开(公告)日：2014-11-11

    申请号：US14134047

    申请日：2013-12-19

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Tetsuya Kakehata ,  Hideto Ohnuma ,  Yoshiaki Yamamoto ,  Kenichiro Makino

    IPC: H01L27/12 ,  H01L29/02 ,  H01L29/786 ,  H01L31/0352 ,  H01L29/06 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66

    CPC classification number: H01L27/1218 ,  H01L21/76254 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/0649 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L31/0352

    Abstract: An object is to provide an SOI substrate provided with a semiconductor layer which can be used practically even when a glass substrate is used as a base substrate. Another object is to provide a semiconductor device having high reliability using such an SOI substrate. An altered layer is formed on at least one surface of a glass substrate used as a base substrate of an SOI substrate to form the SOI substrate. The altered layer is formed on at least the one surface of the glass substrate by cleaning the glass substrate with solution including hydrochloric acid, sulfuric acid or nitric acid. The altered layer has a higher proportion of silicon oxide in its composition and a lower density than the glass substrate.

    Abstract translation: 本发明的目的是提供一种具有半导体层的SOI衬底，即使在使用玻璃衬底作为基底衬底时也可以实际使用。 另一个目的是提供一种使用这种SOI衬底具有高可靠性的半导体器件。 在用作SOI衬底的基底衬底的玻璃衬底的至少一个表面上形成改变的层，以形成SOI衬底。 通过用包括盐酸，硫酸或硝酸的溶液清洗玻璃基板，在玻璃基板的至少一个表面上形成改变的层。 改变的层在其组成中具有较高比例的氧化硅，并且具有比玻璃基底更低的密度。

    Semiconductor device and manufacturing method thereof
    30.
    发明授权
    Semiconductor device and manufacturing method thereof 有权
    半导体装置及其制造方法

    公开(公告)号：US08847483B2

    公开(公告)日：2014-09-30

    申请号：US13892438

    申请日：2013-05-13

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hideaki Kuwabara ,  Hideto Ohnuma

    IPC: H01L33/06 ,  H01L27/32 ,  H01L33/36 ,  H01L51/00

    CPC classification number: H01L51/56 ,  H01L27/3241 ,  H01L27/3246 ,  H01L27/3258 ,  H01L27/3262 ,  H01L33/36 ,  H01L51/0011 ,  H01L51/52 ,  H01L2251/5338

    Abstract: As a result of miniaturization of a pixel region associated with an improvement in definition and an increase in a substrate size associated with an increase in area, defects due to precision, bending, and the like of a mask used at the time of evaporation have become issues. A partition including portions with different thicknesses over a pixel electrode (also referred to as a first electrode) in a display region and in the vicinity of a pixel electrode layer is formed, without increasing the number of steps, by using a photomask or a reticle provided with an auxiliary pattern having a light intensity reduction function made of a diffraction grating pattern or a semi-transmissive film.

    Abstract translation: 由于与清晰度的改善相关联的像素区域的小型化以及与面积的增加相关联的基板尺寸的增加，由于在蒸发时使用的掩模的精度，弯曲等的缺陷已经变成 问题 通过使用光掩模或掩模版形成在显示区域和像素电极层附近的像素电极（也称为第一电极）上具有不同厚度的部分，而不增加步骤数 具有由衍射光栅图案或半透射膜构成的具有光强度降低功能的辅助图案。

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