公开(公告)号：US20250054523A1

公开(公告)日：2025-02-13

申请号：US18932891

申请日：2024-10-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takuro KANEMURA ,  Tatsunori INOUE

IPC: G11C5/10 ,  G11C11/22 ,  H01L29/66 ,  H01L29/78 ,  H10B53/30

Abstract: A semiconductor device with a small circuit area and low power consumption is provided. The semiconductor device includes first to fourth cells, a current mirror circuit, and first to fourth wirings, and the first to fourth cells each include a first transistor, a second transistor, and a capacitor. In each of the first to fourth cells, a first terminal of the first transistor is electrically connected to a first terminal of the capacitor and a gate of the second transistor. The first wiring is electrically connected to first terminals of the second transistors in the first cell and the second cell, the second wiring is electrically connected to first terminals of the second transistors in the third cell and the fourth cell, the third wiring is electrically connected to second terminals of the capacitors in the first cell and the third cell, and the fourth wiring is electrically connected to second terminals of the capacitors in the second cell and the fourth cell. The current mirror circuit is electrically connected to the first wiring and the second wiring.

公开(公告)号：US20220343954A1

公开(公告)日：2022-10-27

申请号：US17640452

申请日：2020-09-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi AOKI ,  Munehiro KOZUMA ,  Masashi FUJITA ,  Takahiko ISHIZU

IPC: G11C7/06 ,  G11C7/08 ,  G11C11/4091 ,  G11C11/54

Abstract: A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.

公开(公告)号：US20220276834A1

公开(公告)日：2022-09-01

申请号：US17625392

申请日：2020-06-29

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takuro KANEMURA

IPC: G06F7/544 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C11/405 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/4096

Abstract: A semiconductor device which can efficiently perform reading of a weight coefficient and a product-sum operation is provided. The semiconductor device includes a product-sum operation circuit and a memory device. The product-sum operation circuit is formed using transistors formed on a semiconductor substrate, and a memory cell of the memory device is formed using an OS transistor provided to be stacked above the semiconductor substrate. The semiconductor device includes a plurality of product-sum operation units where the product-sum operation circuit and the memory cell of the memory device are electrically connected to each other. In each of the product-sum operation units, a weight coefficient stored in the memory cell can be read and a product-sum operation can be performed.

公开(公告)号：US20220262953A1

公开(公告)日：2022-08-18

申请号：US17628091

申请日：2020-07-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Munehiro KOZUMA ,  Takahiko ISHIZU ,  Takeshi AOKI ,  Masashi FUJITA ,  Kazuma FURUTANI ,  Kousuke SASAKI

IPC: H01L29/786 ,  H01L27/108 ,  G11C7/10 ,  G11C7/12 ,  G11C7/14 ,  G06F7/544

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a CPU and an accelerator. The accelerator includes a first memory circuit and an arithmetic circuit. The first memory circuit includes a first transistor. The first transistor includes a semiconductor layer containing a metal oxide in a channel formation region. The arithmetic circuit includes a second transistor. The second transistor includes a semiconductor layer containing silicon in a channel formation region. The first transistor and the second transistor are provided to be stacked. The CPU includes a CPU core including a flip-flop provided with a backup circuit. The backup circuit includes a third transistor. The third transistor includes a semiconductor layer containing a metal oxide in a channel formation region.

公开(公告)号：US20220254401A1

公开(公告)日：2022-08-11

申请号：US17617969

申请日：2020-06-08

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Yoshiyuki KUROKAWA ,  Munehiro KOZUMA ,  Takeshi AOKI

IPC: G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G01N33/00 ,  G01V3/02

Abstract: A semiconductor device resistant to a high temperature with low power consumption is provided. The semiconductor device includes a first and a second circuit, a first and a second cell, and a first and a second wiring. The first cell includes a first transistor, and the second cell includes a second transistor. The first and the second transistor operate in a subthreshold region. The first cell is electrically connected to the first circuit through the first wiring, the first cell is electrically connected to the second circuit through the second wiring, and the second cell is electrically connected to the second circuit through the second wiring. The first cell sets a current flowing through the first transistor to a first current and the second cell sets a current flowing through the second transistor to a second current. At this time, a potential corresponding to the second current is input from the second wiring to the first cell. Then, a third current flows from the second circuit to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the amount of the potential change and the first current.

公开(公告)号：US20220190398A1

公开(公告)日：2022-06-16

申请号：US17439436

申请日：2020-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takayuki IKEDA ,  Takeshi AOKI ,  Munehiro KOZUMA ,  Kei TAKAHASHI ,  Shunpei YAMAZAKI

IPC: H01M10/42

Abstract: A semiconductor device with reduced power consumption is provided. With three transistors, potentials of two nodes are switched and a voltage is detected. One of a source and a drain of a first transistor is electrically connected to a first terminal. The other of the source and the drain of the first transistor is electrically connected to a non-inverting input of a comparator through a first node. One of a source and a drain of a second transistor is electrically connected to a second terminal. The other of the source and the drain of the second transistor is electrically connected to one of a source and a drain of a third transistor through a second node. The other of the source and the drain of the third transistor is electrically connected to a third terminal. A first capacitor is provided between the first node and the second node. An inverting input of the comparator is electrically connected to a fourth terminal. An output of the comparator is electrically connected to a fifth terminal.

公开(公告)号：US20210326117A1

公开(公告)日：2021-10-21

申请号：US17359859

申请日：2021-06-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shintaro HARADA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI

IPC: G06F7/544 ,  H01L29/786 ,  G06N3/04 ,  G06N3/063

Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

公开(公告)号：US20200343245A1

公开(公告)日：2020-10-29

申请号：US16765398

申请日：2018-11-22

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Hiroki INOUE ,  Shintaro HARADA ,  Daisuke MATSUBAYASHI

IPC: H01L27/105 ,  H01L27/12 ,  H01L23/34 ,  H01L29/786

Abstract: Provided is a storage device that achieves both retention operation at high temperatures and high-speed operation at low temperatures.The storage device includes a driver circuit and a plurality of memory cells, and the memory cell includes a transistor and a capacitor; the transistor includes a metal oxide in a channel formation region. In the case where the transistor includes a first gate and a second gate, the driver circuit has a function of driving the second gate, and the driver circuit outputs a potential corresponding to the temperature of the storage device or the temperature of an environment where the storage device is placed to the second gate in a period during which the memory cell retains data.

公开(公告)号：US20180129556A1

公开(公告)日：2018-05-10

申请号：US15784669

申请日：2017-10-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takeshi AOKI ,  Yoshiyuki KUROKAWA

IPC: G06F11/10

CPC classification number: G06F11/1004

Abstract: Data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit. The digital-analog converter circuit has a function of applying voltages as first signals to the first memory cell and the second memory cell. Even when a soft error occurs in the first memory cell or the second memory cell, the storage device has a function of recovering data corrupted by the soft error because the sense circuit selects and outputs a higher one of the voltages applied to the first memory cell and the second memory cell.

公开(公告)号：US20160293649A1

公开(公告)日：2016-10-06

申请号：US15177460

申请日：2016-06-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yoshiyuki KUROKAWA ,  Takayuki IKEDA ,  Hikaru TAMURA ,  Munehiro KOZUMA ,  Masataka IKEDA ,  Takeshi AOKI

IPC: H01L27/146 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378 ,  H01L29/786 ,  H01L31/105

CPC classification number: H01L27/14616 ,  H01L27/14603 ,  H01L27/14632 ,  H01L27/14636 ,  H01L27/14643 ,  H01L29/7869 ,  H01L31/1055 ,  H04N5/361 ,  H04N5/374 ,  H04N5/378

Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.