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    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE
    3.
    发明公开
    LOGIC CIRCUIT FORMED USING UNIPOLAR TRANSISTOR, AND SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240364343A1

    公开(公告)日：2024-10-31

    申请号：US18766726

    申请日：2024-07-09

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Hiroki INOUE ,  Munehiro KOZUMA ,  Takeshi AOKI ,  Shuji FUKAI ,  Fumika AKASAWA ,  Shintaro HARADA ,  Sho NAGAO

    IPC: H03K19/094 ,  H01L27/06

    CPC classification number: H03K19/094 ,  H01L27/0629

    Abstract: A semiconductor device using unipolar transistors, in which high and low levels are expressed using high and low power supply potentials, is provided. The semiconductor device includes four transistors, two capacitors, two wirings, two input terminals, and an output terminal. A source or a drain of the first transistor and a source or a drain of the fourth transistor are electrically connected to the first wiring. A gate of the fourth transistor is electrically connected to the first input terminal, and a gate of the second transistor is electrically connected to the second input terminal. A source or a drain of the second transistor and a source or a drain of the third transistor are electrically connected to the second wiring. The first transistor, the second transistor, and the two capacitors are electrically connected to the output terminal.

    SEMICONDUCTOR DEVICE AND SYSTEM USING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND SYSTEM USING THE SAME 有权

    公开(公告)号：US20210326117A1

    公开(公告)日：2021-10-21

    申请号：US17359859

    申请日：2021-06-28

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shintaro HARADA ,  Yoshiyuki KUROKAWA ,  Takeshi AOKI

    IPC: G06F7/544 ,  H01L29/786 ,  G06N3/04 ,  G06N3/063

    Abstract: A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.

    DETECTING DEVICE AND SEMICONDUCTOR DEVICE
    10.
    发明申请
    DETECTING DEVICE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20210359669A1

    公开(公告)日：2021-11-18

    申请号：US17286091

    申请日：2019-10-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Shintaro HARADA ,  Takayuki IKEDA

    IPC: H03K3/037 ,  G01R31/3835 ,  G01R31/36 ,  G06F1/06

    Abstract: The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which “H” is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal.

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