公开(公告)号：US20170125456A1

公开(公告)日：2017-05-04

申请号：US15407287

申请日：2017-01-17

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiro KASAHARA

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  G02F2001/136236 ,  H01L21/28008 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2227/323

Abstract: The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film.

公开(公告)号：US20160011473A1

公开(公告)日：2016-01-14

申请号：US14861280

申请日：2015-09-22

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Takahiro KASAHARA

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/134336 ,  G02F1/134309 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134345 ,  G02F2201/52 ,  G09G3/3607 ,  G09G3/3611 ,  G09G3/3614 ,  G09G3/3659 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/1266 ,  H01L27/3213 ,  H01L27/3218 ,  H01L27/326 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78654 ,  H01L51/5284

Abstract: A new TFT arrangement is demonstrated, which enables prevention of TFT to be formed over a joint portion between the adjacent SOI layers prepared by the process including the separation of a thin single crystal semiconductor layer from a semiconductor wafer. The TFT arrangement is characterized by the structure where a plurality of TFTs each belonging to different pixels is gathered and arranged close to an intersection portion of a scanning line and a signal line. This structure allows the distance between regions, which are provided with the plurality of TFTs, to be extremely large compared with the distance between adjacent TFTs in the conventionalTFT arrangement in which all TFTs are arranged in at a regular interval. The formation of a TFT over the joint portion can be avoided by the present arrangement, which leads to the formation of a display device with a negligible amount of display defects.

公开(公告)号：US20150311235A1

公开(公告)日：2015-10-29

申请号：US14795602

申请日：2015-07-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/127 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/24 ,  H01L29/7869

Abstract: A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode.

Abstract translation: 需要包括具有适当结构和占用面积小的氧化物半导体，保护电路等的显示装置。 保护电路使用非线性元件形成，该非线性元件包括覆盖栅电极的栅极绝缘膜; 在所述栅极绝缘层上方并与所述栅电极重叠的第一氧化物半导体层; 以及通过层叠导电层和第二氧化物半导体层而形成的第一布线层和第二布线层，并且其端部在第一氧化物半导体层上方并与栅电极重叠。 非线性元件的栅电极连接到扫描线或信号线，非线性元件的第一布线层或第二布线层直接连接到栅极电极层，以施加电位 栅电极。

公开(公告)号：US20150236054A1

公开(公告)日：2015-08-20

申请号：US14700562

申请日：2015-04-30

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/12 ,  H01L29/786

Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, and a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the first oxide semiconductor layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

Abstract translation: 保护电路包括非线性元件，其包括栅电极，覆盖栅电极的栅极绝缘层，与栅极绝缘层上的栅电极重叠的第一氧化物半导体层，以及第一布线层和第二布线层 其端部与第一氧化物半导体层上的栅电极重叠，并且其中层叠有导电层和第二氧化物半导体层。 在栅极绝缘层上，具有不同性质的氧化物半导体层彼此结合，由此可以进行与肖特基结的稳定操作。 因此，可以降低结漏电，提高非线性元件的特性。

公开(公告)号：US20140302670A1

公开(公告)日：2014-10-09

申请号：US14219752

申请日：2014-03-19

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiro KASAHARA

IPC: H01L21/28

CPC classification number: H01L27/1288 ,  G02F1/1368 ,  G02F2001/136236 ,  H01L21/28008 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/3262 ,  H01L29/66969 ,  H01L29/7869 ,  H01L2227/323

Abstract: The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film.

Abstract translation: 在半导体器件的制造工艺中使用的掩模和光刻工艺的数量减少。 第一导电膜形成在衬底上; 在第一导电膜上形成第一绝缘膜; 在第一绝缘膜上形成半导体膜; 通过蚀刻半导体膜的一部分形成包括沟道区的半导体膜; 在半导体膜上形成第二绝缘膜; 在第二绝缘膜上形成掩模; 通过使用掩模去除与半导体膜重叠的第二绝缘膜的第一部分和与半导体膜不重叠的第一绝缘膜和第二绝缘膜的第二部分; 去除面具; 并且在所述第二绝缘膜的至少一部分上形成与所述半导体膜电连接的第二导电膜。

公开(公告)号：US20130134417A1

公开(公告)日：2013-05-30

申请号：US13731649

申请日：2012-12-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L29/20

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L27/127 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/24 ,  H01L29/7869

Abstract: A display device including an oxide semiconductor, a protective circuit and the like having appropriate structures and a small occupied area is necessary. The protective circuit is formed using a non-linear element which includes a gate insulating film covering a gate electrode; a first oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode; and a first wiring layer and a second wiring layer each of which is formed by stacking a conductive layer and a second oxide semiconductor layer and whose end portions are over the first oxide semiconductor layer and overlap with the gate electrode. The gate electrode of the non-linear element is connected to a scan line or a signal line, the first wiring layer or the second wiring layer of the non-linear element is directly connected to the gate electrode layer so as to apply potential of the gate electrode.

公开(公告)号：US20240363639A1

公开(公告)日：2024-10-31

申请号：US18766834

申请日：2024-07-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/12 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1214 ,  G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/66742 ,  H01L29/7869 ,  H01L29/78693 ,  G02F1/13624

Abstract: A protective circuit includes a non-linear element, which includes a gate electrode, a gate insulating layer covering the gate electrode, a pair of first and second wiring layers whose end portions overlap with the gate electrode over the gate insulating layer and in which a second oxide semiconductor layer and a conductive layer are stacked, and a first oxide semiconductor layer which overlaps with at least the gate electrode and which is in contact with the gate insulating layer, side face portions and part of top face portions of the conductive layer and side face portions of the second oxide semiconductor layer in the first wiring layer and the second wiring layer. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be decreased and the characteristics of the non-linear element can be improved.

公开(公告)号：US20200176489A1

公开(公告)日：2020-06-04

申请号：US16782455

申请日：2020-02-05

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD

Inventor： Takahiro KASAHARA

IPC: H01L27/12 ,  H01L21/28 ,  H01L29/66 ,  H01L29/786

Abstract: The number of masks and photolithography processes used in a manufacturing process of a semiconductor device are reduced. A first conductive film is formed over a substrate; a first insulating film is formed over the first conductive film; a semiconductor film is formed over the first insulating film; a semiconductor film including a channel region is formed by etching part of the semiconductor film; a second insulating film is formed over the semiconductor film; a mask is formed over the second insulating film; a first portion of the second insulating film that overlaps the semiconductor film and second portions of the first insulating film and the second insulating film that do not overlap the semiconductor film are removed with the use of the mask; the mask is removed; and a second conductive film electrically connected to the semiconductor film is formed over at least part of the second insulating film.

公开(公告)号：US20190081031A1

公开(公告)日：2019-03-14

申请号：US16189396

申请日：2018-11-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kengo AKIMOTO ,  Shigeki KOMORI ,  Hideki UOCHI ,  Tomoya FUTAMURA ,  Takahiro KASAHARA

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/786

Abstract: A protective circuit includes a non-linear element which includes a gate electrode, a gate insulating layer covering the gate electrode, a first oxide semiconductor layer overlapping with the gate electrode over the gate insulating layer, a channel protective layer overlapping with a channel formation region of the first oxide semiconductor layer, and a pair of a first wiring layer and a second wiring layer whose end portions overlap with the gate electrode over the channel protective layer and in which a conductive layer and a second oxide semiconductor layer are stacked. Over the gate insulating layer, oxide semiconductor layers with different properties are bonded to each other, whereby stable operation can be performed as compared with Schottky junction. Thus, the junction leakage can be reduced and the characteristics of the non-linear element can be improved.

公开(公告)号：US20170168575A1

公开(公告)日：2017-06-15

申请号：US15366200

申请日：2016-12-01

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Takahiro KASAHARA ,  Hideaki KUWABARA

IPC: G06F3/01 ,  G06F1/16 ,  G09G5/38 ,  G06F3/0488 ,  G06F3/041

Abstract: An input device having flexibility includes a display portion, a touch panel, a haptic element, a haptic controller, and a control portion. The touch panel is configured to acquire information on the size of a user's body part operating the input device and transmit the information to the control portion. The control portion is configured to receive the information, generate information on the positioning of a plurality of buttons, and transmit the information to the display portion. The display portion is configured to display the plurality of buttons on the basis of the received information. The haptic controller is configured to transmit information on a haptic effect to the haptic element.