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    HETEROJUNCTION SEMICONDUCTOR DEVICE HAVING HIGH BLOCKING CAPABILITY
    21.
    发明申请
    HETEROJUNCTION SEMICONDUCTOR DEVICE HAVING HIGH BLOCKING CAPABILITY 有权

    公开(公告)号：US20210234030A1

    公开(公告)日：2021-07-29

    申请号：US16969437

    申请日：2019-10-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Weifeng SUN ,  Siyang LIU ,  Sheng LI ,  Chi ZHANG ,  Xinyi TAO ,  Ningbo LI ,  Longxing SHI

    IPC: H01L29/778

    Abstract: A heterojunction semiconductor device comprises a substrate; a second barrier layer is disposed on the second channel layer and a second channel is formed; a trench gate structure is disposed in the second barrier layer; the trench gate structure is embedded into the second barrier layer and is composed of a gate medium and a gate metal located in the gate medium; an isolation layer is disposed in the second channel layer and separates the second channel layer into an upper layer and a lower layer; a first barrier layer is disposed between the lower layer of the second channel layer and the first channel layer and a first channel is formed; a bottom of the metal drain is flush with a bottom of the first barrier layer; and a first metal source is disposed between the second metal source and the first channel layer.

    GATE DRIVE CIRCUIT FOR REDUCING REVERSE RECOVERY CURRENT OF POWER DEVICE
    22.
    发明申请
    GATE DRIVE CIRCUIT FOR REDUCING REVERSE RECOVERY CURRENT OF POWER DEVICE 有权

    公开(公告)号：US20210218396A1

    公开(公告)日：2021-07-15

    申请号：US17044623

    申请日：2020-04-15

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Jing ZHU ,  Weifeng SUN ,  Bowei YANG ,  Siyuan YU ,  Yangyang LU ,  Longxing SHI ,  Shengli LU

    IPC: H03K17/687 ,  H03K19/20

    Abstract: The present invention discloses a gate drive circuit for reducing a reverse recovery current of a power device, and belongs to the field of basic electronic circuit technologies. The gate drive circuit includes a high-voltage LDMOS transistor, a diode forming a freewheeling path when the diode is turned on or a low-voltage MOS transistor in anti-parallel connection with a body diode, and a voltage detection circuit. When the power device is turned off, a freewheeling current produced by an inductive load flows through a freewheeling diode, the voltage detection circuit detects that the freewheeling diode is turned on, and an output signal is processed by a control circuit, to cause the drive circuit to output a high level, so that channels of the power device and the high-voltage LDMOS transistor are turned on, the freewheeling current flows through the conductive channels, almost not through the freewheeling diode, and there is no reverse recovery current in the freewheeling diode at this time, thereby reducing the reverse recovery current of the power device.

    MULTI-PHASE HIGH-PRECISION CURRENT SHARING CONTROL METHOD APPLIED TO CONSTANT ON-TIME CONTROL
    24.
    发明公开
    MULTI-PHASE HIGH-PRECISION CURRENT SHARING CONTROL METHOD APPLIED TO CONSTANT ON-TIME CONTROL 审中-公开

    公开(公告)号：US20240266943A1

    公开(公告)日：2024-08-08

    申请号：US18641384

    申请日：2024-04-21

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Shen XU ,  Haiqing ZHANG ,  Yujie LIU ,  Ruizhi WANG ,  Yuan GAO ,  Yongjia LI ,  Weifeng SUN ,  Longxing SHI

    IPC: H02M1/08 ,  H02M1/00 ,  H02M3/158

    CPC classification number: H02M1/082 ,  H02M1/0025 ,  H02M3/1586

    Abstract: A multi-phase high-precision current sharing control method applied to constant on-time control is provided, wherein a current difference between continuously sampled current of each line and mean current is processed by a PI compensation module and a low-pass filter module to obtain on-time regulation data. A high bit of the regulation data controls the value of counter reference Vref in an on-time control module, and a low bit controls the length of an enabled delay line in a delay line module. The counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of a DPWM. The method takes COT control of a Buck converter as a typical application. Compared with a multi-phase COT controller without a current-sharing mechanism, the method can improve the stability and reliability of the system.

    HIGH-THRESHOLD POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    25.
    发明申请
    HIGH-THRESHOLD POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220367716A1

    公开(公告)日：2022-11-17

    申请号：US17762929

    申请日：2021-01-20

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Siyang LIU ,  Weifeng SUN ,  Chi ZHANG ,  Shuxuan XIN ,  Shen LI ,  Le QIAN ,  Chen GE ,  Longxing SHI

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/812 ,  H01L29/778

    Abstract: The present invention discloses a high-threshold power semiconductor device and a manufacturing method thereof. The high-threshold power semiconductor device includes, in sequence from bottom to top: a metal drain electrode, a substrate, a buffer layer, and a drift region; further including: a composite column body which is jointly formed by a drift region protrusion, a columnar p-region and a columnar n-region on the drift region, a channel layer, a passivation layer, a dielectric layer, a heavily doped semiconductor layer, a metal gate electrode and a source metal electrode. The composite column body is formed by sequentially depositing a p-type semiconductor layer and an n-type semiconductor layer on the drift region and then etching same. The channel layer and the passivation layer are formed in sequence by deposition. Thus, the above devices are divided into a cell region and a terminal region. The dielectric layer, the heavily doped semiconductor layer, the metal gate electrode and the source metal electrode only exist in the cell region, and the passivation layer of the terminal region extends upwards and is wrapped outside the channel layer. This structure can increase a threshold voltage of the device, improve the blocking characteristics of the device and reduce the size of a gate capacitance.

    LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT
    26.
    发明申请
    LATERAL INSULATED GATE BIPOLAR TRANSISTOR WITH LOW TURN-ON OVERSHOOT CURRENT 有权

    公开(公告)号：US20220157975A1

    公开(公告)日：2022-05-19

    申请号：US17606216

    申请日：2020-03-31

    Applicant: SOUTHEAST UNIVERSITY

    Inventor： Jing ZHU ,  Ankang LI ,  Long ZHANG ,  Weifeng SUN ,  Shengli LU ,  Longxing SHI

    IPC: H01L29/739 ,  H01L29/10

    Abstract: A lateral insulated gate bipolar transistor (IGBT) with a low turn-on overshoot current is provided to reduce a peak value of a current flowing through a device during turn-on of a second gate pulse while preventing a current capability and a withstand voltage capability from being degraded. The lateral IGBT includes: a buried oxygen arranged on a P-type substrate, an N-type drift region arranged on the buried oxygen, on which a P-type body region and an N-type buffer region are arranged, a P-type collector region arranged in the N-type buffer region, a field oxide layer arranged above the N-type drift region, a P-type well region arranged in the P-type body region, and a P-type emitter region and an emitter region arranged in the P-type well region, where inner boundaries of the foregoing 4 regions are synchronously recessed to form a pinch-off region. A gate oxide layer is arranged on a surface of the P-type body region, and a polysilicon gate is arranged on the gate oxide layer. The polysilicon gate includes a first gate located above the surface of the P-type body region and a second gate located above the pinch-off region and the N-type drift region. The first gate is connected to a first gate resistor, and the second gate is connected to a second gate resistor.

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