公开(公告)号：US20220173736A1

公开(公告)日：2022-06-02

申请号：US17531654

申请日：2021-11-19

Applicant: STMicroelectronics International N.V.

Inventor： Vaibhav Garg ,  Abhishek Jain ,  Anand Kumar

IPC: H03K17/687

Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.

公开(公告)号：US10862487B2

公开(公告)日：2020-12-08

申请号：US16674207

申请日：2019-11-05

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Nitin Gupta ,  Nitin Jain

IPC: H03L1/00 ,  H03L7/183 ,  H03L7/087 ,  H03L7/085

Abstract: A circuit includes a frequency detector generating a comparison signal as a function of a comparison between a reference signal and a feedback signal. An oscillator generates an output signal as a function of the comparison signal. A frequency divider, in operation, divides the output signal by a division value to produce the feedback signal as having a frequency that is a multiple of a frequency of the reference signal. A frequency counter circuit measures the frequency of the reference signal and generates a count signal based thereupon. A control circuit adjusts the division value used by the frequency divider, in operation, based upon the count signal.

公开(公告)号：US10348314B2

公开(公告)日：2019-07-09

申请号：US15888153

申请日：2018-02-05

Applicant: STMicroelectronics International N.V.

Inventor： Anand Kumar ,  Gagan Midha

IPC: H03L7/089 ,  H03C3/09 ,  H03L7/093 ,  H03L7/099 ,  H03L7/197 ,  H04B15/04

Abstract: A phase or frequency locked-loop circuit includes an oscillator configured to generate an output clock signal having a frequency set by an oscillator control signal. A modulator circuit receives a first signal and a second signal and is configured to generate a control signal having a value modulated in response to the first and second signals. A filter circuit generates the oscillator control signal by filtering the control signal. A delta-sigma modulator circuit operates to modulate the second signal in response to a modulation profile. As a result, the output clock signal is a spread spectrum clock signal.

公开(公告)号：US09325324B1

公开(公告)日：2016-04-26

申请号：US14573002

申请日：2014-12-17

Applicant: STMicroelectronics International N.V.

Inventor： Nitin Gupta ,  Anand Kumar ,  Abhirup Lahiri

IPC: H03L7/00 ,  H03L1/02 ,  H03L7/093 ,  H03L7/18 ,  H03L7/099 ,  H03L7/107

CPC classification number: H03L7/099 ,  H03L1/00 ,  H03L7/0895 ,  H03L7/0898 ,  H03L7/0995 ,  H03L7/1072 ,  H03L7/113 ,  H03L7/18

Abstract: A phase locked loop (PLL) circuit includes a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control signal responsive to the phase comparison and an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback signal is derived from said output signal. The PLL circuit further operates in a calibration mode of operation wherein the oscillator circuit operates in a frequency locked loop mode to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit across process, voltage and temperature in response to the frequency comparison. Furthermore, bias current for a charge pump within the phase comparison circuit is calibrated during calibration mode of operation to match a temperature independent reference current.

Abstract translation: 锁相环（PLL）电路包括相位比较电路，其被配置为将输入信号的相位与反馈信号的相位进行比较，并响应于相位比较产生控制信号，以及振荡器电路，被配置为产生频率的输出信号 由所述控制信号设置，其中所述反馈信号从所述输出信号导出。 PLL电路进一步在校准操作模式下工作，其中振荡器电路以频率锁定环路模式操作，以将输入信号的频率与输出信号的频率进行比较，并将振荡器电路的增益集中在过程，电压和温度之间 响应频率比较。 此外，相位比较电路内的电荷泵的偏置电流在校准操作模式下进行校准，以匹配与温度无关的参考电流。