-
21.发明授权公开(公告)号：US11342031B2
公开(公告)日：2022-05-24
申请号：US17006510
申请日：2020-08-28
Inventor： Marco Pasotti , Dario Livornesi , Roberto Bregoli , Vikas Rana , Abhishek Mittal
Abstract: An integrated circuit includes a memory array and a read voltage regulator that generates read voltages from the memory array. The read voltage regulator includes a replica memory cell and the replica bitline current path. The replica memory cell is a replica of memory cells of the memory array. The replica bitline current path is a replica of current paths associated with deadlines of the memory array. The read voltage regulator generates a read voltage based on the current passed through the replica bitline current path. This read voltage is then supplied to the wordlines of the memory array during a read operation.
-
公开(公告)号：US20210234460A1
公开(公告)日：2021-07-29
申请号：US17145107
申请日：2021-01-08
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
IPC: H02M3/07
Abstract: A voltage supply circuit and a method for controlling a voltage supply circuit are provided. The voltage supply circuit includes a positive charge pump stage that generates a positive voltage and a negative charge pump stage that generates a negative voltage. The voltage supply circuit also includes a control stage that compares a voltage representative of the negative voltage with a reference voltage and causes a slope of the positive voltage to decrease when the voltage representative of the negative voltage exceeds the reference voltage.
-
公开(公告)号：US10049736B2
公开(公告)日：2018-08-14
申请号：US15433795
申请日：2017-02-15
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
-
公开(公告)号：US09634562B1
公开(公告)日：2017-04-25
申请号：US15177830
申请日：2016-06-09
Inventor： Vikas Rana , Marco Pasotti , Fabio De Santis
CPC classification number: H02M3/073
Abstract: A voltage doubler circuit supports operation in a positive voltage boosting mode to positively boost voltage from a first node to a second node and operation in a negative voltage boosting mode to negatively boost voltage from the second node to the first node. The voltage doubler circuits receive two clock signals having different high voltage levels. A series of voltage doubler circuit are connected in a charge pump with controllable operation in the first and second modes. A connecting circuit interconnects the first and second nodes of the voltage doubler circuits to provide a first connection path, with a first input voltage, to support the positive voltage boosting mode operation and a second connection path, with a proper input voltage, to support the negative voltage boosting mode. A discharge circuit is provided to discharge the voltage doubler circuits when operation of the charge pump circuit is terminated.
-
公开(公告)号：US09613696B1
公开(公告)日：2017-04-04
申请号：US14971345
申请日：2015-12-16
Inventor： Marco Pasotti , Marcella Carissimi , Vikas Rana
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/0026 , G11C2013/0078
Abstract: An integrated circuit includes an array of phase-change memory (PCM) cells, and bitlines coupled to the array of PCM cells. The integrated circuit also includes a first decoder circuit having a respective plurality of transistors having a first conductivity type being coupled together and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM cell. In addition, the integrated circuit includes a second decoder circuit having a plurality of transistors having a second conductivity type being coupled together and to the given bitline and configured to discharge the given bitline at an end of the program current pulse.
-
Patent Agency Ranking
公开(公告)号：US20170047909A1
公开(公告)日：2017-02-16
申请号：US14826017
申请日：2015-08-13
Inventor： Vikas Rana , Fabio De Santis
IPC: H03K3/012 , H03K17/687
CPC classification number: H03K17/102
Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
Abstract translation: 提供了共源共栅电压发生电路和方法。 该电路包括四个开关元件。 在高电压运行模式中，第一和第二开关元件分别将第一中间电压输入节点耦合到第一中间电压输出节点，将第二中间电压输入节点耦合到第二中间电压输出节点。 在低电压操作模式中，第三开关元件将第一和第二中间电压输入节点耦合到接地参考电压电平，第四开关元件将第一和第二中间电压输出节点耦合到电源电压电平。
-
公开(公告)号：US09755632B2
公开(公告)日：2017-09-05
申请号：US14826017
申请日：2015-08-13
Inventor： Vikas Rana , Fabio De Santis
CPC classification number: H03K17/102
Abstract: A cascode voltage generating circuit and method are provided. The circuit includes four switching elements. In a high voltage operation mode, the first and second switching elements, respectively, couple a first intermediate voltage input node to a first intermediate voltage output node, and a second intermediate voltage input node to a second intermediate voltage output node. In a low voltage operation mode, the third switching element couples the first and second intermediate voltage input nodes to a ground reference voltage level, and the fourth switching element couples the first and second intermediate voltage output nodes to a supply voltage level.
-
公开(公告)号：US20160099033A1
公开(公告)日：2016-04-07
申请号：US14506865
申请日：2014-10-06
Inventor： Abhishek Lal , Vikas Rana , Marco Pasotti
Abstract: A memory includes a column decoder performing at least two levels of decoding using a first level decoder that decodes between the column bit lines and first level decode lines and a second level decoder that decodes between the first level decode lines and second level decode lines. The second level decoder includes first transistors coupled between the first level decode lines and read output lines and second transistors coupled between the first level decode lines and write input lines. The first transistors have a first voltage rating and are driven by decode control signals referenced to a low supply voltage compatible with the first voltage rating. The second transistors have a second voltage rating, higher than the first voltage rating, and are driven by decode control signals referenced to a high supply voltage (in excess of the low supply voltage) compatible with the second voltage rating.
Abstract translation: 存储器包括列解码器，其使用在列位线和第一电平解码线之间解码的第一电平解码器和在第一电平解码线和第二电平解码线之间解码的第二电平解码器来执行解码的至少两个级别。 第二电平解码器包括耦合在第一电平解码线和读出输出线之间的第一晶体管和耦合在第一电平解码线和写输入线之间的第二晶体管。 第一晶体管具有第一电压额定值，并且由与第一额定电压兼容的低电源电压参考的解码控制信号驱动。 第二晶体管具有高于第一电压额定值的第二电压额定值，并且由与第二额定电压兼容的高电源电压（超过低电源电压）的解码控制信号驱动。
-
29.发明授权Non-volatile memory with reduced sub-threshold leakage during program and erase operations 有权在编程和擦除操作期间具有减少的亚阈值泄漏的非易失性存储器公开(公告)号：US09159425B2
公开(公告)日：2015-10-13
申请号：US14089016
申请日：2013-11-25
Inventor： Vikas Rana , Ganesh Raj R , Fabio De Santis
CPC classification number: G11C16/0433
Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.
Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。
-
30.发明申请NON-VOLATILE MEMORY WITH REDUCED SUB-THRESHOLD LEAKAGE DURING PROGRAM AND ERASE OPERATIONS 有权在程序和擦除操作期间具有降低的次级阈值漏电的非易失性存储器公开(公告)号：US20150146490A1
公开(公告)日：2015-05-28
申请号：US14089016
申请日：2013-11-25
Inventor： Vikas Rana , Ganesh Raj R , Fabio De Santis
IPC: G11C16/14
CPC classification number: G11C16/0433
Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.
Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。
-
-
-
-
-
-
-
-
-
Search Results
60
records
(took 0.018 seconds)
