公开(公告)号：US10386411B2

公开(公告)日：2019-08-20

申请号：US15684334

申请日：2017-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Manish Sharma

IPC: G01R31/317 ,  G01R31/3185

Abstract: A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

公开(公告)号：US20190094301A1

公开(公告)日：2019-03-28

申请号：US15712778

申请日：2017-09-22

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Satinder Singh Malhi

IPC: G01R31/3185 ,  G01R31/04 ,  H01L21/66

Abstract: A scan chain collects scan chain data from testing of a functional circuit and outputs a scan chain signal containing the scan chain data. A voltage monitor circuit operates to compare a supply voltage against a threshold and assert a reset signal when the supply voltage crosses the threshold. The reset signal resets a flip flop circuit whose output signal controls operation of a logic circuit that blocks passage of the scan chain signal to an integrated circuit probe pad and instead applies a constant logic signal to the probe pad indicating a voltage monitoring error.

公开(公告)号：US20190064268A1

公开(公告)日：2019-02-28

申请号：US16170479

申请日：2018-10-25

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3193 ,  G01R31/3177 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

CPC classification number: G01R31/31727 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31922 ,  G01R31/31937 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

Abstract: A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.

公开(公告)号：US10151797B2

公开(公告)日：2018-12-11

申请号：US15223061

申请日：2016-07-29

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Tripti Gupta

IPC: G01R31/3185

Abstract: A logic built-in self-test (LBIST) circuit implements a pipeline scan enable launch on shift (LOS) feature. A first scan chain flip-flop has a scan enable input configured to receive a first scan enable signal. A logic circuit has a first input coupled to a data output of the first scan chain flip-flop and a second input coupled to receive the first scan enable signal. A second scan chain flip-flop has a scan input coupled to a scan output of the first scan chain flip-flop. A scan enable input of the second scan chain flip-flop is coupled to receive a second scan enable signal generated at an output of the logic circuit. The first and second scan chain flip-flops are clocked by a same clock signal.

公开(公告)号：US20180080987A1

公开(公告)日：2018-03-22

申请号：US15268848

申请日：2016-09-19

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Nimit Endlay ,  Balwinder Singh Soni

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31722 ,  G01R31/31723 ,  G01R31/31724 ,  G01R31/3177 ,  G01R31/31937 ,  G06F11/25 ,  G06F11/26 ,  G06F11/27

Abstract: A test circuit receives LBIST and ATPG mode signals, and generates a first output as high when in ATPG or LBIST, and a second output as low when in ATPG or LBIST. A multiplexing circuit receives an ATPG clock and functional clock, and outputs one. A clock gate circuit includes a first latch receiving the second output, and an enable input receiving an inverse of the ATPG clock or functional clock. A second latch receives the first output, and has an enable input receiving the inverse of the ATPG clock or functional clock. The clock gate circuit includes a first AND gate receiving output of the first latch and ATPG clock or functional clock, a second AND gate receiving output of the second latch and the ATPG clock or LBIST clock, and an OR gate receiving outputs of the first and second AND gates, and generating a test clock.

公开(公告)号：US20180013418A1

公开(公告)日：2018-01-11

申请号：US15615178

申请日：2017-06-06

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Srinivas Dhulipalla

IPC: H03K17/22 ,  H03K19/20 ,  H03K5/19

CPC classification number: H03K17/223 ,  G01R31/2832 ,  G06F1/24 ,  G06F1/30 ,  H03K5/19 ,  H03K17/22 ,  H03K19/20

Abstract: A power management circuit includes both a power on reset (POR) circuit and a voltage monitoring circuit. Explicit testing of these circuits is accomplished by controlling voltages applied to the circuits and monitoring an output signal responsive to a logical combination of outputs from the POR circuit and voltage monitoring circuit. The applied voltages are controlled with respect to timing of application, fixing of voltages and varying of voltages in a manner where a certain one of the circuits for explicit test is isolated with change in logic state of the output signal being indicative of operation of that isolated circuit.

公开(公告)号：US20240427366A1

公开(公告)日：2024-12-26

申请号：US18337720

申请日：2023-06-20

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Shiv Kumar Vats ,  Umesh Chandra Srivastava

IPC: G06F1/06

Abstract: According to an embodiment, a method for testing a scan chain is provided. The method includes receiving a first clock signal and a first scan enable signal and generating a second and third clock signal based on the first clock signal and the first scan enable signal. The third clock signal is delayed by a clock pulse from the second clock signal. The first, second, and third clock signal have the same duty cycle. The method further includes providing the second clock signal and the second scan enable signal to, respectively, a clock terminal and scan enable input of a first scan flip-flop of the scan chain. The method further includes providing the third clock signal and a third scan enable signal to, respectively, a clock terminal and a scan enable input of a last scan flip-flop of the scan chain.

公开(公告)号：US20240264229A1

公开(公告)日：2024-08-08

申请号：US18165602

申请日：2023-02-07

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Gourav Garg

IPC: G01R31/317 ,  H03K19/0175

CPC classification number: G01R31/31721 ,  H03K19/017509

Abstract: According to an embodiment, a method for testing multiple power-on-resets in a system-on-chip with a multi-power domain architecture operating under a dual power flow mode is provided. The method includes powering up the system-on-chip to full power mode, decoupling a third power domain from a first power domain and a second power domain, monitoring a general purpose input/output (GPIO) pad of the third power domain during a ramping down of a supply of the third power domain, and detecting a logic transition at the GPIO pad of the third power domain corresponding to a trip-point of the power-on-reset of the third power domain.

公开(公告)号：US12020760B2

公开(公告)日：2024-06-25

申请号：US18078714

申请日：2022-12-09

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Balwinder Singh Soni ,  Avneep Kumar Goyal

IPC: G11C29/00 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C29/38 ,  G11C29/12 ,  H03K19/20

CPC classification number: G11C29/38 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/1206 ,  G11C2029/3602 ,  H03K19/20

Abstract: Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

公开(公告)号：US11983025B2

公开(公告)日：2024-05-14

申请号：US17967498

申请日：2022-10-17

Applicant: STMicroelectronics International N.V.

Inventor： Venkata Narayanan Srinivasan ,  Mayankkumar Hareshbhai Niranjani ,  Dhulipalla Phaneendra Kumar ,  Gourav Garg ,  Sourabh Banzal

IPC: G05F1/10 ,  G05F1/46 ,  G05F3/02 ,  H03K19/20

CPC classification number: G05F1/46 ,  H03K19/20

Abstract: An electric device includes: a first power domain; a second power domain; a third power domain, where during power-up, the third, the second, and the first power domains are configured to be powered up sequentially, where during standby-exit, the first, the second, and the third power domains are configured to be powered up sequentially; isolation paths that provide controlled signal transmission among the first, the second, and the third power domains, where each isolation path includes an isolation circuit between an input power domain and an output power domain of the isolation path; and a control circuit in the first power domain, where for each isolation path, the control circuit is configured to generate an isolation control signal for the isolation circuit, where the isolation circuit is configured enable or disable signal transmission along the isolation path.