公开(公告)号：US20160035765A1

公开(公告)日：2016-02-04

申请号：US14706858

申请日：2015-05-07

Applicant: Samsung Display Co., Ltd.

Inventor： Seung-Ho YOON ,  Su-Bin BAE ,  Yu-Gwang JEONG

IPC: H01L27/12

CPC classification number: H01L27/1288 ,  H01L27/124 ,  H01L29/4908

Abstract: A method of fabricating metal wiring, including: sequentially forming first and second conductive layers on a substrate; forming a first photosensitive film pattern on the first and second conductive layers; forming first and second conductive patterns by etching parts of the first and second conductive layers by using the first photosensitive film pattern as a mask; forming a second photosensitive film pattern positioned inside the first photosensitive film pattern by a predetermined interval by ashing the first photosensitive film pattern; etching an exposed first conductive pattern by using the second photosensitive film pattern as a mask; and removing the second photosensitive film pattern.

Abstract translation: 一种制造金属布线的方法，包括：在基板上依次形成第一和第二导电层; 在所述第一和第二导电层上形成第一感光膜图案; 通过使用第一感光膜图案作为掩模来蚀刻第一和第二导电层的部分来形成第一和第二导电图案; 通过灰化所述第一感光膜图案形成位于所述第一感光膜图案内的预定间隔的第二感光膜图案; 通过使用第二感光膜图案作为掩模蚀刻暴露的第一导电图案; 并去除第二感光膜图案。

公开(公告)号：US20240292667A1

公开(公告)日：2024-08-29

申请号：US18519369

申请日：2023-11-27

Applicant: Samsung Display Co., LTD.

Inventor： Hyun Eok SHIN ,  Dong Min LEE ,  Woo-Seok JEON ,  Yung Bin CHUNG ,  Yu-Gwang JEONG

IPC: H10K59/122 ,  H10K59/12 ,  H10K59/80

CPC classification number: H10K59/122 ,  H10K59/1201 ,  H10K59/80522

Abstract: A display device includes a plurality of transistors disposed on a substrate, an insulating layer disposed on the transistors, a first electrode disposed on the insulating layer and electrically connected to the transistors, a partition wall disposed on the insulating layer, a common layer disposed on the partition wall and the first electrode, an emission layer disposed on the common layer, a second electrode disposed on the emission layer, and an auxiliary layer disposed on the second electrode. The partition wall includes a groove, and an inner width of the groove is greater than an inlet width of the groove.

公开(公告)号：US20240016012A1

公开(公告)日：2024-01-11

申请号：US18321621

申请日：2023-05-22

Applicant: Samsung Display Co., LTD.

Inventor： DAWOON JUNG ,  Yu-Gwang JEONG ,  Su Bin BAE ,  Tae Wook KANG

IPC: H10K59/131 ,  H10K59/12 ,  H10K59/124

CPC classification number: H10K59/131 ,  H10K59/1201 ,  H10K59/124

Abstract: A display device includes: a substrate; a semiconductor on the substrate; a first gate insulating layer on the semiconductor; a gate electrode on the first gate insulating layer, and overlapping with the semiconductor; a signal line spaced from the gate electrode; a sacrificial layer on the signal line, and including an amorphous silicon material; an interlayer insulating layer on the gate electrode and the sacrificial layer; a source electrode on the interlayer insulating layer, and connected to a first region of the semiconductor; a drain electrode on the interlayer insulating layer, and connected to a second region of the semiconductor; and a connecting member on the interlayer insulating layer, and connected to the signal line.

公开(公告)号：US20220384549A1

公开(公告)日：2022-12-01

申请号：US17817329

申请日：2022-08-03

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yu-Gwang JEONG ,  Taewook KANG ,  Wooyong SUNG

IPC: H01L27/32 ,  H01L51/56 ,  H01L51/52 ,  H01L51/00 ,  H01L51/50

Abstract: A method of manufacturing a display panel includes providing an insulating substrate that includes a hole area, a display area that surrounds the hole area, and a peripheral area adjacent to the display area, forming a semiconductor pattern in the display area, forming an insulating layer, forming contact holes in the insulating layer that expose portions of the semiconductor pattern, and forming a module hole by etching a portion of the insulating layer and a portion of the insulating substrate that overlap the hole area.

公开(公告)号：US20220229322A1

公开(公告)日：2022-07-21

申请号：US17713715

申请日：2022-04-05

Applicant: Samsung Display Co., LTD.

Inventor： Seon-Il KIM ,  Sung Won CHO ,  Sang Gab KIM ,  Su Bin BAE ,  Yu-Gwang JEONG ,  Dae Won CHOI

IPC: G02F1/1368 ,  G02F1/1362 ,  H01L51/56 ,  H01L51/52 ,  H01L27/32

Abstract: A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 Å to about 300 Å, and a thickness of the main conductive layer is in a range of about 1,000 Å to about 20,000 Å.

公开(公告)号：US20220068979A1

公开(公告)日：2022-03-03

申请号：US17212812

申请日：2021-03-25

Applicant: Samsung Display Co., Ltd.

Inventor： Dae Soo KIM ,  Yu-Gwang JEONG ,  Sung Won CHO

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/311 ,  H01L21/3065

Abstract: A method for etching an insulating layer includes: sequentially forming a first gate insulating layer, an amorphous silicon layer, a first interlayer insulating layer, and a second interlayer insulating layer on a substrate; applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process; first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas used in the first etching.

公开(公告)号：US20210384287A1

公开(公告)日：2021-12-09

申请号：US17445471

申请日：2021-08-19

Applicant: Samsung Display Co., Ltd. ,  POSTECH ACADEMY-INDUSTRY FOUNDATION

Inventor： Sang Gab KIM ,  Hyun Min CHO ,  Tae Sung KIM ,  Yu-Gwang JEONG ,  Su Bin BAE ,  Jin Seock KIM ,  Sang Gyun KIM ,  Hyo Min KO ,  Kil Won CHO ,  Hansol LEE

IPC: H01L27/32

Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

公开(公告)号：US20170317104A1

公开(公告)日：2017-11-02

申请号：US15380596

申请日：2016-12-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang JEONG ,  Hyun Min CHO ,  Su Bin BAE ,  Shin II CHOI ,  Sang Gab KIM

IPC: H01L27/12 ,  H01L21/311 ,  H01L27/32 ,  G02F1/1368

CPC classification number: H01L27/124 ,  G02F1/1368 ,  G02F2201/123 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/1218 ,  H01L27/1288 ,  H01L27/3246 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/41733

Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.

公开(公告)号：US20160320876A1

公开(公告)日：2016-11-03

申请号：US14925439

申请日：2015-10-28

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Ha SON ,  Jae Neung KIM ,  Yong-Hwan RYU ,  Yun Jong YEO ,  Joo Hyung LEE ,  Yu-Gwang JEONG

IPC: G06F3/044

CPC classification number: G06F3/044 ,  G06F3/0416 ,  G06F2203/04102 ,  G06F2203/04103

Abstract: A touch sensor includes a touch substrate including a touch sensing area and a non-sensing area outside the touch sensing area, touch electrodes disposed in the touch sensing area and configured to sense a touch, and touch wiring connected to the touch electrodes in the non-sensing area, in which the touch wiring includes a first wiring conductive layer, a second wiring conductive layer disposed on the first wiring conductive layer, and transparent layers disposed at first and second sides of the second wiring conductive layer and on the first wiring conductive layer.

Abstract translation: 触摸传感器包括触摸基板，其包括触摸感测区域和触摸感测区域外部的非感测区域，触摸电极设置在触摸感测区域中并且被配置为感测触摸，并且触摸连接到非触摸电极中的触摸电极的布线， 其中所述触摸布线包括第一布线导电层，布置在所述第一布线导电层上的第二布线导电层以及设置在所述第二布线导电层的第一和第二侧以及所述第一布线导电层上的透明层 层。

公开(公告)号：US20150053989A1

公开(公告)日：2015-02-26

申请号：US14455113

申请日：2014-08-08

Applicant: Samsung Display Co., Ltd.

Inventor： Yu-Gwang JEONG ,  Shin-Il CHOI ,  Su-Bin BAE ,  Dae-Ho KIM ,  Sang-Gab KIM ,  Jae-Neung KIM

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/3065

CPC classification number: H01L27/124 ,  H01L21/31116 ,  H01L21/76804 ,  H01L21/76832 ,  H01L27/1259

Abstract: A display substrate includes a base substrate, a common line on the base substrate, a first insulation layer covering the common line and having a first insulating material, a conductive pattern on the first insulation layer and including a source electrode and a drain electrode, a second insulation layer covering the drain electrode and the common line, and including a lower second insulation layer having a second insulating material and an upper second insulation layer having the first insulating material, a first electrode electrically connected to the drain electrode through a first contact hole in the second insulation layer, and a second electrode electrically connected to the common line through a second contact hole in the first and second insulation layers. The upper and lower second insulation layers on the drain electrode have a first hole and a second hole respectively that form the first contact hole.

Abstract translation: 显示基板包括基底基板，基底基板上的公共线，覆盖公共线的第一绝缘层，并具有第一绝缘材料，第一绝缘层上的导电图案，包括源电极和漏电极， 覆盖漏电极和公共线的第二绝缘层，并且包括具有第二绝缘材料的下第二绝缘层和具有第一绝缘材料的上第二绝缘层，第一电极，通过第一接触孔电连接到漏电极 以及通过第一绝缘层和第二绝缘层中的第二接触孔与公共线电连接的第二电极。 漏电极上的上，下第二绝缘层分别具有形成第一接触孔的第一孔和第二孔。