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    Display device
    22.
    发明授权
    Display device 有权

    公开(公告)号：US11227875B2

    公开(公告)日：2022-01-18

    申请号：US16836651

    申请日：2020-03-31

    Applicant: Samsung Display Co., Ltd.

    Inventor： Myoung Hwa Kim ,  Joon Seok Park ,  So Young Koo ,  Tae Sang Kim ,  Yeon Keon Moon ,  Geun Chul Park ,  Jun Hyung Lim ,  Kyung Jin Jeon

    IPC: H01L27/00 ,  H01L29/00 ,  H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66 ,  G09G3/32 ,  H01L27/32

    Abstract: A display device includes a pixel connected to a scan line, and a data line crossing the scan line, wherein the pixel includes a light-emitting element, a driving transistor configured to control a driving current supplied to the light-emitting element according to a data voltage applied from the data line, and a first switching transistor configured to apply the data voltage of the data line to the driving transistor according to a scan signal that is applied to the scan line. The driving transistor includes a first active layer including an oxide semiconductor, and a first oxide layer disposed on the first active layer and including an oxide semiconductor. The first switching transistor includes a second active layer including an oxide semiconductor, and the first oxide layer is not disposed on the second active layer.

    DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
    25.
    发明申请
    DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20200286927A1

    公开(公告)日：2020-09-10

    申请号：US16783002

    申请日：2020-02-05

    Applicant: Samsung Display Co., LTD.

    Inventor： Joon Seok Park ,  Tae Sang Kim ,  Yeon Keon Moon ,  Geun Chul Park ,  Jun Hyung Lim ,  Kyung Jin Jeon

    IPC: H01L27/12

    Abstract: A display device includes a plurality of pixels respectively coupled to scan lines and data lines intersecting the scan lines, wherein at least some of the pixels includes a driving transistor including a substrate, a first insulating layer disposed on the substrate, a first active layer disposed on the first insulating layer, a first gate electrode disposed on the first active layer, and a first source electrode and a first drain electrode electrically connected to the first active layer, the first drain electrode being spaced apart from the first source electrode by a first distance, and a switching transistor including a second gate electrode disposed between the substrate and the first insulating layer, a second active layer disposed on the same layer as the first active layer, and a second source electrode and a second drain electrode electrically connected to the second active layer, the second drain electrode being spaced apart from the second source electrode by a second distance different from the first distance.

    Thin film transistor array panel
    26.
    发明授权
    Thin film transistor array panel 有权
    薄膜晶体管阵列面板

    公开(公告)号：US09543336B2

    公开(公告)日：2017-01-10

    申请号：US14963769

    申请日：2015-12-09

    Applicant: Samsung Display Co., Ltd.

    Inventor： Masataka Kano ,  Ji Hun Lim ,  Yeon Keon Moon ,  Jun Hyung Lim ,  So Young Koo ,  Myoung Hwa Kim

    IPC: H01L27/14 ,  H01L29/04 ,  H01L29/15 ,  H01L31/036 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/788

    CPC classification number: H01L27/1248 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/788

    Abstract: A thin-film transistor array panel includes a substrate, a first gate electrode disposed on the substrate, a first self-assembled monolayer disposed on the first gate electrode, a gate insulating layer disposed on the first self-assembled monolayer, a semiconductor disposed on the gate insulating layer, a drain electrode overlapping the semiconductor, the drain electrode being separated from and facing a source electrode with respect to the semiconductor, a first interlayer insulating layer disposed on the source electrode and the drain electrode, a second self-assembled monolayer disposed on the first interlayer insulating layer, a second gate electrode disposed on the second self-assembled monolayer, a second interlayer insulating layer disposed on the second gate electrode, and a pixel electrode disposed on the second interlayer insulating layer and connected to the drain electrode.

    Abstract translation: 薄膜晶体管阵列面板包括基板，设置在基板上的第一栅极电极，设置在第一栅电极上的第一自组装单层，设置在第一自组装单层上的栅极绝缘层，设置在第一自组装单层上的半导体 所述栅极绝缘层，与所述半导体重叠的漏电极，所述漏电极相对于所述半导体分离并面对源电极，设置在所述源电极和所述漏电极上的第一层间绝缘层，第二自组装单层 设置在第一层间绝缘层上的第二栅电极，设置在第二自组装单层上的第二栅电极，设置在第二栅电极上的第二层间绝缘层，以及设置在第二层间绝缘层上并连接到漏极的像素电极 。

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