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公开(公告)号：US20240322048A1
公开(公告)日：2024-09-26
申请号：US18606081
申请日：2024-03-15
发明人： Kyunghwan LEE , Jeonil LEE , Minhee CHO , Daweon HA
IPC分类号： H01L29/792 , H10B12/00
CPC分类号： H01L29/7926 , H10B12/482 , H10B12/485 , H10B12/488
摘要： Provided is an integrated circuit device including a source line extending in a first horizontal direction on a substrate, a channel layer extending in a vertical direction, disposed on the source line, and having a first sidewall and a second sidewall, a trapping layer on the first sidewall of the channel layer and including an oxide semiconductor, a word line on at least one sidewall of the trapping layer and extending in a second horizontal direction crossing the first horizontal direction, a gate insulation layer between the at least one sidewall of the trapping layer and the word line, and a bit line electrically connected to the channel layer and extending in the first horizontal direction, wherein the channel layer has a first bandgap energy, and the trapping layer has a second bandgap energy that is greater than the first bandgap energy.
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公开(公告)号：US20240191932A1
公开(公告)日：2024-06-13
申请号：US18583013
申请日：2024-02-21
发明人： Kyunghwan LEE , Youngdeog KOH , Jihwan CHUN , Heecheol KANG , Kwangjoo KIM , Jinju KIM , Minkyung LEE
IPC分类号： F25D23/00 , B23K26/359 , B41M5/00 , C23F1/36 , C25D11/04
CPC分类号： F25D23/00 , B41M5/0058 , C23F1/36 , C25D11/04 , B23K26/359 , F25D2323/06
摘要： A manufacturing method of an aluminum exterior panel including preparing an aluminum material; machining to shape an edge of the aluminum material; implementing a fine multilayered pattern on a surface of the processed aluminum material; forming of forming fine corrugations on the surface of the aluminum material on which the fine multilayered pattern is implemented; anodizing to form pores on the surface of the aluminum material on which the fine corrugations are formed; digital printing of implementing a color and an image on the aluminum material on which the pores are formed; and sealing to close the pores.
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公开(公告)号：US20230389290A1
公开(公告)日：2023-11-30
申请号：US18200135
申请日：2023-05-22
发明人： Jeonil LEE , Kyunghwan LEE , Min Hee CHO
CPC分类号： H10B12/315 , H10B12/482 , H10B12/485 , H10B53/10 , H10B53/30 , H01L29/0847
摘要： A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.
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公开(公告)号：US20230380176A1
公开(公告)日：2023-11-23
申请号：US18102349
申请日：2023-01-27
发明人： Daewon HA , Kyunghwan LEE , Youngnam Hwang
摘要： A semiconductor device includes a cell region including a plurality of memory cells, and a peripheral circuit region controlling the plurality of memory cells. Each of the plurality of memory cells includes a first active region and a second active region adjacent to each other, a first channel layer and a second channel layer extending in the first direction, connected to the first active region and the second active region, and separated from each other in the third direction, a first ferroelectric layer and a first gate electrode layer sequentially provided on the first channel layer, and a second ferroelectric layer and a second gate electrode layer sequentially provided on the second channel layer. The first gate electrode layer and the second gate electrode layer are separated from each other in the third direction.
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公开(公告)号：US20230292522A1
公开(公告)日：2023-09-14
申请号：US18055974
申请日：2022-11-16
发明人： Daewon HA , Kyunghwan LEE , Hyunmog PARK
IPC分类号： H01L21/02
摘要： A three-dimensional non-volatile memory device includes a memory cell array including a plurality of memory cells repeatedly arranged in a first lateral direction, a second lateral direction, and a vertical direction on a substrate. The first lateral direction and the second lateral direction are parallel to a main surface of the substrate and perpendicular to each other, and the vertical direction is perpendicular to the main surface of the substrate. The memory cell array includes a plurality of horizontal channel regions and a vertical word line. The plurality of horizontal channel regions extend in the first lateral direction on the substrate. The plurality of horizontal channel regions overlap each other and are apart from each other in the vertical direction. The vertical word line passes through the plurality of horizontal channel regions in the vertical direction.
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公开(公告)号：US20230180453A1
公开(公告)日：2023-06-08
申请号：US18054986
申请日：2022-11-14
发明人： Hyuncheol KIM , Yongseok KIM , Kyunghwan LEE , Minjun LEE , Daewon HA
IPC分类号： H01L27/108
CPC分类号： H01L27/10802
摘要： A memory device is provided. The memory device includes a substrate, a fin structure on the substrate, a gate structure on the fin structure, a first source/drain at one end of the fin structure, and a second source/drain at the other end of the fin structure, wherein the gate structure includes a trap layer, a blocking layer, and a gate electrode layer sequentially stacked on the fin structure, the first source/drain is doped with or has incorporated therein dopants of a first conductivity-type, and the second source/drain is doped with or has incorporated therein dopants of a second conductivity-type dopants that are different from the dopants of the first conductivity-type.
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公开(公告)号：US20230101700A1
公开(公告)日：2023-03-30
申请号：US17881747
申请日：2022-08-05
发明人： Kyunghwan LEE , Yongseok KIM , Hyuncheol KIM , Jongman PARK , Dongsoo WOO , Minjun LEE
IPC分类号： H01L27/108
摘要： A semiconductor memory device may include first and second bit lines spaced apart from each other, an interlayer insulating layer covering the first and second bit lines and including a groove extending to cross both of the first and second bit lines, a first channel pattern connected to the first bit line and in contact with an inner side surface of the groove and covering a top surface of the interlayer insulating layer, a second channel pattern connected to the second bit line and in contact with an opposite inner side surface of the groove and covering the top surface of the interlayer insulating layer, a word line in the groove, first and second electrodes on the interlayer insulating layer and in contact with the first and second channel patterns, respectively, and a dielectric layer between the first and second electrodes.
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公开(公告)号：US20220004874A1
公开(公告)日：2022-01-06
申请号：US17480859
申请日：2021-09-21
摘要： A method and an electronic apparatus for training a personal model of a user are provided. The method includes obtaining first information including personal data of the user represented as a first constituent element of the personal model; obtaining second information including group data of a plurality of users in a group to which the user belongs, represented as a second constituent element of the personal model; determining a first weight value and a second weight value to be respectively applied to the first information and the second information based on reliability of the first information; and training the personal model based on the first information and the second information to which the first weight value and the second weight value are respectively applied.
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公开(公告)号：US20210225842A1
公开(公告)日：2021-07-22
申请号：US16999378
申请日：2020-08-21
发明人： Hyuncheol KIM , Yongseok KIM , Satoru YAMADA , Sungwon YOO , Kyunghwan LEE , Jaeho HONG
IPC分类号： H01L27/102 , H01L29/24
摘要： A semiconductor memory device may include a first electrode and a second electrode, which are spaced apart from each other in a first direction, and a first semiconductor pattern, which is in contact with both of the first and second electrodes. The first semiconductor pattern may include first to fourth sub-semiconductor patterns, which are sequentially disposed in the first direction. The first and fourth sub-semiconductor patterns may be in contact with the first and second electrodes, respectively. The first and third sub-semiconductor patterns may be of a first conductivity type, and the second and fourth sub-semiconductor patterns may be of a second conductivity type different from the first conductivity type. Each of the first to fourth sub-semiconductor patterns may include a transition metal and a chalcogen element.
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公开(公告)号：US20210164111A1
公开(公告)日：2021-06-03
申请号：US17108280
申请日：2020-12-01
发明人： Kyunghwan LEE , Kwangjoo KIM , Jinju KIM , Jiyoung SONG
摘要： A pattern forming method is disclosed. The pattern forming method includes buffing a surface of a product containing aluminum, masking at least a part of the buffed surface with an etching resist, etching a part of the buffed surface not masked by the etching resist, removing the etching resist from the surface, and anodizing the surface from which the etching resist is removed.
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