公开(公告)号：US11705166B2

公开(公告)日：2023-07-18

申请号：US17182357

申请日：2021-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10

CPC classification number: G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C2207/105

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

公开(公告)号：US10672436B2

公开(公告)日：2020-06-02

申请号：US16058709

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10

Abstract: A memory device includes; a first memory chip including a first on-die Termination (ODT) circuit comprising a first ODT resistor, a second memory chip including a second ODT circuit comprising a second ODT resistor, at least one chip enable signal pin that receives at least one chip enable signal, wherein the at least one chip enable signal selectively enables at least one of the first memory chip and the second memory chip, and an ODT pin commonly connected to the first memory chip and the second memory chip that receives an ODT signal, wherein the ODT signal defines an enable period for at least one of the first ODT circuit and the second ODT circuit, and in response to the ODT signal and the at least one chip enable signal, one of the first ODT resistor and the second ODT resistor is enabled to terminate a signal received by at least one of the first memory chip and the second memory chip.

公开(公告)号：US20200091021A1

公开(公告)日：2020-03-19

申请号：US16357674

申请日：2019-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min-Jae Lee ,  Sang-Lok Kim ,  Byung-Hoon Jeong ,  Tae-Sung Lee ,  Jeong-Don Ihm ,  Jae-Yong Jeong ,  Young-Don Choi

IPC: H01L21/66 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.

公开(公告)号：US10559373B2

公开(公告)日：2020-02-11

申请号：US16458933

申请日：2019-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/06

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10291275B2

公开(公告)日：2019-05-14

申请号：US15397012

申请日：2017-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo Lee ,  Byung-Hoon Jeong ,  Jeong-Don Ihm ,  Young-Don Choi

IPC: H03F1/32 ,  H03F1/34 ,  H04B1/24 ,  H04L25/03 ,  H04L12/863 ,  H04L25/02 ,  H04L12/861

Abstract: A reception interface circuit includes a termination circuit, a buffer and an interface controller. The termination circuit is configured to change a termination mode in response to a termination control signal. The buffer is configured to change a reception characteristic in response to a buffer control signal. The interface controller is configured to generate the termination control signal and the buffer control signal such that the reception characteristic of the buffer is changed in association with the change in the termination mode. The reception interface circuit may support various communication standards by changing the reception characteristic of the buffer in association with the termination mode. Using the reception interface circuit, communication efficiency of transceiver systems such as a memory system and/or compatibility between a transmitter device and a receiver device may be improved.

公开(公告)号：US08553486B2

公开(公告)日：2013-10-08

申请号：US13675064

申请日：2012-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byung-Hoon Jeong

IPC: G11C17/18 ,  G11C17/00 ,  G11C29/00

CPC classification number: G11C17/16 ,  G11C7/20 ,  G11C2029/0411

Abstract: A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.