公开(公告)号：US11804270B2

公开(公告)日：2023-10-31

申请号：US17460954

申请日：2021-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Yeon Shin ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Jung-June Park

IPC: G11C16/30 ,  G11C7/10 ,  G11C16/26 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: G11C16/30 ,  G11C7/1051 ,  G11C16/26 ,  H10B41/27 ,  H10B41/35 ,  H10B41/40 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A non-volatile memory device includes a memory cell region including a first metal pad and a memory cell array including a plurality of memory cells, and a peripheral circuit region including a second metal pad and an output driver to output a data signal, and vertically connected to the memory cell region by the first metal pad and the second metal pad. The output driver includes a pull-up driver and a pull-down driver. The pull-up driver includes a first pull-up driver having a plurality of P-type transistors and a second pull-up driver having a plurality of N-type transistors. The pull-down driver includes a plurality of N-type transistors. One or more power supply voltages having different voltage levels are selectively applied to the pull-up driver. A first power supply voltage is applied to the first pull-up driver, and a second power supply voltage is applied to the second pull-up driver.

公开(公告)号：US10937471B2

公开(公告)日：2021-03-02

申请号：US16933768

申请日：2020-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C11/4096 ,  G11C7/22 ,  G11C11/4076 ,  G11C5/06 ,  G11C16/26

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10741225B2

公开(公告)日：2020-08-11

申请号：US16802084

申请日：2020-02-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Su Jang ,  Man-Jae Yang ,  Jeong-Don Ihm ,  Go-Eun Jung ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C16/26 ,  G11C5/06

Abstract: A non-volatile memory device includes a serial pipeline structure connected to an output stage of a First In, First Out (FIFO) memory. The FIFO memory is configured to store data transmitted through a data path having a wave pipeline structure based on a plurality of FIFO input clock signals and output the stored data based on a plurality of FIFO output clock signals. A serializer is configured to output data to an input/output pad based on a select clock signal. The serial pipeline structure is connected between the FIFO memory and the serializer and configured to compensate for a phase difference between the data output from the FIFO memory and the select clock signal.

公开(公告)号：US10340022B2

公开(公告)日：2019-07-02

申请号：US15977553

申请日：2018-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: H03K19/177 ,  G11C29/02 ,  G11C7/10 ,  G11C5/06 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US11742040B2

公开(公告)日：2023-08-29

申请号：US17704345

申请日：2022-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C16/06 ,  G11C29/02 ,  G11C5/06 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C29/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/06 ,  G11C16/102 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：USRE49206E1

公开(公告)日：2022-09-06

申请号：US16692483

申请日：2019-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Woon Kang ,  Jeong-don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: H03K19/0175 ,  G11C7/00 ,  H03H7/38 ,  G11C5/02 ,  G11C5/04 ,  G11C7/10 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/02 ,  H03K19/00 ,  G11C16/04 ,  G11C29/50

Abstract: A nonvolatile memory device includes a first memory structure. The first memory structure includes first through N-th memory dies that may be connected to an external memory controller via a first channel. N is a natural number equal to or greater than two. At least one of the first through N-th memory dies is configured to be used as a first representative die that performs an on-die termination (ODT) operation while a data write operation is performed for one of the first through N-th memory dies.

公开(公告)号：US20130070548A1

公开(公告)日：2013-03-21

申请号：US13675064

申请日：2012-11-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Hoon Jeong

IPC: G11C29/52

CPC classification number: G11C17/16 ,  G11C7/20 ,  G11C2029/0411

Abstract: A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

Abstract translation: 描述半导体存储器件及其操作方法。 半导体存储器件包括具有存储第一熔丝数据的多个第一反熔丝元件的第一反熔丝阵列，具有存储纠错码（ECC）数据的多个第二反熔丝元件的第二反熔丝阵列 与ECC解码器配置成通过使用ECC数据校正第一熔丝数据来生成第二熔丝数据。

公开(公告)号：US12073898B2

公开(公告)日：2024-08-27

申请号：US18361132

申请日：2023-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C5/06 ,  G11C7/10 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C29/02

CPC classification number: G11C29/025 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/06 ,  G11C16/102 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US11342038B2

公开(公告)日：2022-05-24

申请号：US17161995

申请日：2021-01-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-Ji Kim ,  Jung-June Park ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C16/26 ,  G11C16/06 ,  G11C29/02 ,  G11C5/06 ,  G11C16/10

Abstract: A nonvolatile memory (NVM) device includes a data pin, a control pin, an on-die termination (ODT) pin, and a plurality of NVM memory chips commonly connected to the data pin and the control pin. A first NVM chip among the NVM chips includes an ODT circuit. The first NVM chip determines one of an ODT write mode and an ODT read mode based on a control signal received through the control pin and an ODT signal received through the ODT pin, uses the ODT circuit to perform an ODT on the data pin during the ODT write mode, and uses the ODT circuit to perform the ODT on the control pin during the ODT read mode.

公开(公告)号：US10438635B2

公开(公告)日：2019-10-08

申请号：US16113500

申请日：2018-08-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Kyoo Lee ,  Dae-Hoon Na ,  Jeong-Don Ihm ,  Byung-Hoon Jeong ,  Young-Don Choi

IPC: G11C7/10 ,  G11C7/06 ,  H01L25/065 ,  G11C7/22 ,  H01L23/00

Abstract: An apparatus includes data transmitter having first through N-th data drivers configured to provide first through N-th data signals, respectively, and a strobe driver configured to provide a strobe signal, and a data receiver having a strobe buffer configured to generate a control signal based on the strobe signal, and first through N-th sense amplifiers configured to sense N-bit data based on the control signal, a reference signal and the first through N-th data signals. The bus includes a strobe TSV configured to connect the strobe driver with the strobe buffer, and first through N-th data TSVs configured to connect the first through N-th data drivers with the first through N-th sense amplifiers, respectively. A reference signal supplier controls the reference signal such that a discharge speed of the reference signal is slower than a discharge speed of each of the first through N-th data signals during data transmission.