公开(公告)号：US11804280B2

公开(公告)日：2023-10-31

申请号：US17749607

申请日：2022-05-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C16/28 ,  G11C7/10 ,  G11C8/18 ,  G11C29/44 ,  G11C29/12

CPC classification number: G11C29/50004 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/18 ,  G11C16/28 ,  G11C29/44 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.

公开(公告)号：US20230055963A1

公开(公告)日：2023-02-23

申请号：US17710283

申请日：2022-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yongsung CHO ,  Kyoman Kang ,  Minhwi Kim ,  Ilhan Park ,  Jinyoung Chun

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/26

Abstract: A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells; a page buffer circuit connected to the memory cell array through a plurality of bit lines and including a page buffer connected to each of the plurality of bit lines, the page buffer including at least one first latch for storing data based on a voltage level of a first sensing node; and a control circuit configured to adjust a level of a voltage signal provided to the page buffer circuit. The page buffer includes a trip control transistor arranged between the at least one first latch and the first sensing node, and wherein the control circuit is further configured to, based on a read operation being performed on the memory cell array, control a trip control voltage to be provided to a gate of the trip control transistor. A level of the trip control voltage varies according to a temperature of the memory device.

公开(公告)号：US11527293B2

公开(公告)日：2022-12-13

申请号：US17341837

申请日：2021-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Park ,  Kyunghoon Sung ,  Ilhan Park ,  Jisang Lee ,  Joon Suc Jang ,  Sanghyun Joo

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/10 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.

公开(公告)号：US11514997B2

公开(公告)日：2022-11-29

申请号：US17156801

申请日：2021-01-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Ilhan Park ,  Sangwan Nam

IPC: G11C29/42 ,  G11C29/18 ,  G11C29/44 ,  G11C29/12

Abstract: A controller including: control pins for providing control signals to a nonvolatile memory; a buffer memory configured to store first to third tables; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a history read level and is determined by the first and second offset information, and when the error of the first data is uncorrectable, an on-chip valley search operation is performed by the nonvolatile memory according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information which corresponds to the detection information is generated.

公开(公告)号：US11482263B2

公开(公告)日：2022-10-25

申请号：US17239647

申请日：2021-04-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan Park ,  Jinyoung Kim ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/18 ,  G11C8/08

Abstract: A storage device includes at least one non-volatile memory device and a controller configured to control the at least one non-volatile memory device. The at least one non-volatile memory device performs an on-chip valley search (OVS) operation by latching a read command at an edge of a write enable (WE) signal according to a command latch enable (CLE) signal and an address latch enable (ALE) signal. The controller receives detection information according to the OVS operation from the at least one non-volatile memory device in response to a specific command. The OVS operation includes a first OVS operation using a read level and a second OVS operation using a changed read level.

公开(公告)号：US20220139484A1

公开(公告)日：2022-05-05

申请号：US17353583

申请日：2021-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinyoung Kim ,  Sehwan Park ,  Youngdeok Seo ,  Ilhan Park

IPC: G11C29/42 ,  G11C29/44 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/08 ,  G11C16/24

Abstract: A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.

公开(公告)号：US20220028478A1

公开(公告)日：2022-01-27

申请号：US17147851

申请日：2021-01-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sehwan PARK ,  Jinyoung Kim ,  Ilhan Park ,  Kyoman Kang ,  Sangwan Nam

IPC: G11C29/50 ,  G11C29/44 ,  G11C7/10 ,  G11C8/18

Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.