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公开(公告)号：US11749356B2
公开(公告)日：2023-09-05
申请号：US17450871
申请日：2021-10-14
发明人： Jinyoung Kim , Sehwan Park , Youngdeok Seo , Dongmin Shin
IPC分类号： G11C16/30 , H01L25/065 , H01L25/18 , H01L23/00 , G11C5/14
CPC分类号： G11C16/30 , H01L24/08 , H01L25/0657 , H01L25/18 , G11C5/147 , G11C5/148 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
摘要： A memory system includes a non-volatile memory device including a machine learning (ML) module and a peripheral power management integrated circuit (IC), and a memory controller configured to command the non-volatile memory device to enter an idle mode by providing an external power command to the non-volatile memory device. The machine learning (ML) module configures a neural network and trains the neural network via machine learning, and the peripheral power management IC is configured to generate an internal power command that is different from the external power command based on the external power command and monitoring information corresponding to the ML module.
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公开(公告)号：US11579972B2
公开(公告)日：2023-02-14
申请号：US17399528
申请日：2021-08-11
发明人： Dongmin Shin , Jinyoung Kim , Sehwan Park , Youngdeok Seo
摘要： A controller including a non-volatile memory interface circuit connected to at least one non-volatile memory device and configured to control the at least one non-volatile memory device; an error correction circuit configured to perform an error correction operation on a codeword received from the non-volatile memory interface circuit according to an error correction decoding level from among a plurality of error correction decoding levels, wherein the non-volatile memory interface circuit is further configured to: receive side information from the at least one non-volatile memory device; predict a distribution of memory cells based on the side information; and select the error correction decoding level from among the plurality of error correction decoding levels according to the predicted distribution.
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公开(公告)号：US11682467B2
公开(公告)日：2023-06-20
申请号：US17353583
申请日：2021-06-21
发明人： Jinyoung Kim , Sehwan Park , Youngdeok Seo , Ilhan Park
CPC分类号： G11C29/42 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/3495 , G11C29/4401
摘要： A nonvolatile memory device includes a plurality of memory blocks and a control logic circuit configured to perform a first page on-chip valley search (OVS) operation on memory cells connected to one wordline of a memory block selected in response to an address, among the plurality of memory blocks, in response to a first read command. The control logic circuit is further configured to change a read level of at least one state using detection information of the first page OVS operation, and to perform a second page read operation on the memory cells using the changed read level in response to a second read command.
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公开(公告)号：US11631466B2
公开(公告)日：2023-04-18
申请号：US17239646
申请日：2021-04-25
发明人： Sanghyun Choi , Youngdeok Seo , Kangho Roh
IPC分类号： G06F12/00 , G11C16/26 , G06F3/06 , G06N3/04 , G06N3/08 , G11C16/10 , G11C16/16 , G11C11/56 , G11C16/04
摘要： A storage device performs a read operation by restoring an ON cell count (OCC) from a power loss protection (PLP) area of a nonvolatile memory. The nonvolatile memory includes a memory blocks, a buffer memory and a controller. The buffer memory stores a first ON cell count (OCC1) indicating a number of memory cells turned ON by a first read voltage and a second ON cell count (OCC2) indicating a number of memory cells turned ON by a second read voltage among the memory cells connected to a reference word line. The controller stores the OCC1 for each of the memory blocks in the PLP area when a sudden power off occurs in the storage device.
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公开(公告)号：US11562804B2
公开(公告)日：2023-01-24
申请号：US17469422
申请日：2021-09-08
发明人： Sehwan Park , Jinyoung Kim , Youngdeok Seo , Dongmin Shin , Joonsuc Jang , Sungmin Joe
摘要： A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
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公开(公告)号：US20220222138A1
公开(公告)日：2022-07-14
申请号：US17397321
申请日：2021-08-09
发明人： Sehwan PARK , Jinyoung Kim , Ilhan Park , Youngdeok Seo
摘要： A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.
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公开(公告)号：US11862273B2
公开(公告)日：2024-01-02
申请号：US18068337
申请日：2022-12-19
发明人： Sehwan Park , Jinyoung Kim , Youngdeok Seo , Dongmin Shin , Joonsuc Jang , Sungmin Joe
CPC分类号： G11C29/42 , G11C16/102 , G11C16/26 , G11C29/12015 , G11C29/18 , G11C29/4401 , G11C2029/1202 , G11C2029/1204 , G11C2029/1802
摘要： A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
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公开(公告)号：US11817153B2
公开(公告)日：2023-11-14
申请号：US17503197
申请日：2021-10-15
发明人： Jinyoung Kim , Sehwan Park , Ilhan Park , Youngdeok Seo , Dongmin Shin
CPC分类号： G11C16/16 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/26
摘要： A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.
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9.发明授权公开(公告)号：US11670387B2
公开(公告)日：2023-06-06
申请号：US17328487
申请日：2021-05-24
发明人： Youngdeok Seo , Jinyoung Kim , Sehwan Park , Dongmin Shin
CPC分类号： G11C16/3481 , G06F18/214 , G06N20/10 , G11C16/08 , G11C16/102 , G11C16/26 , G11C16/3404
摘要： A non-volatile memory device includes a memory cell array including memory cells, a page buffer circuit including page buffers respectively connected to bit lines, a buffer memory, and a control logic configured to control a read operation on the memory cells. In the read operation, the control logic obtains valley search detection information including read target block information and word line information by performing a valley search sensing operation on a distribution of threshold voltages of the memory cells, obtains a plurality of read levels using a read information model by inputting the valley search detection information into the read information model, and performs a main sensing operation for the read operation.
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公开(公告)号：US20220254419A1
公开(公告)日：2022-08-11
申请号：US17450871
申请日：2021-10-14
发明人： Jinyoung Kim , Sehwan Park , Youngdeok Seo , Dongmin Shin
IPC分类号： G11C16/30 , H01L25/065 , H01L25/18 , H01L23/00
摘要： A memory system includes a non-volatile memory device including a machine learning (ML) module and a peripheral power management integrated circuit (IC), and a memory controller configured to command the non-volatile memory device to enter an idle mode by providing an external power command to the non-volatile memory device. The machine learning (ML) module configures a neural network and trains the neural network via machine learning, and the peripheral power management IC is configured to generate an internal power command that is different from the external power command based on the external power command and monitoring information corresponding to the ML module.
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