公开(公告)号：US10170366B2

公开(公告)日：2019-01-01

申请号：US15436343

申请日：2017-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Jeong-Hyo Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/49 ,  H01L27/02

Abstract: A semiconductor device is provided as follows. Active fins protrude from a substrate, extending in a first direction. A first device isolation layer is disposed at a first side of the active fins. A second device isolation layer is disposed at a second side of the active fins. A top surface of the second device isolation layer is higher than a top surface of the first device isolation layer and the second side is opposite to the first side. A normal gate extends across the active fins in a second direction crossing the first direction. A first dummy gate extends across the active fins and the first device isolation layer in the second direction. A second dummy gate extends across the second device isolation layer in the second direction.

公开(公告)号：US09935017B2

公开(公告)日：2018-04-03

申请号：US15489782

申请日：2017-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Eung-Gwan Kim ,  Jeong-Yun Lee

IPC: H01L21/02 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/161 ,  H01L29/16 ,  H01L29/165 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/823828 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.

公开(公告)号：US20170194324A1

公开(公告)日：2017-07-06

申请号：US15461934

申请日：2017-03-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Se-Wan PARK ,  Baik-Min SUNG ,  Bo-Cheol JEONG

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

公开(公告)号：US09659827B2

公开(公告)日：2017-05-23

申请号：US14803893

申请日：2015-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Eung-Gwan Kim ,  Jeong-Yun Lee

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L21/823828 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823864 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode is formed on the isolation layer and crossing the first and second fins. Source/drain regions are formed on the first and second fins adjacent the gate electrode. After forming the source/drain regions, a portion of the gate electrode between the first and second fins is removed to expose the isolation layer. The source/drain regions may be formed by epitaxial growth.

公开(公告)号：US10944003B2

公开(公告)日：2021-03-09

申请号：US16816908

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Chang-Hee Kim ,  Sung-Il Park ,  Dong-Hun Lee

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L23/532 ,  H01L21/308 ,  H01L29/423 ,  H01L29/165 ,  H01L21/8234

Abstract: A vFET includes a first impurity region doped with first impurities at an upper portion of the substrate. A first diffusion control pattern is formed on the first impurity region. The first diffusion control pattern is configured to control the diffusion of the first impurities. A channel extends in a vertical direction substantially orthogonal to an upper surface of the substrate. A second impurity region is doped with second impurities on the channel. A second diffusion control pattern is between the channel and the second impurity region. The second diffusion control pattern is configured to control the diffusion of the second impurities. A gate structure is adjacent to the channel.

公开(公告)号：US10692864B2

公开(公告)日：2020-06-23

申请号：US16233301

申请日：2018-12-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Se-Wan Park ,  Baik-Min Sung ,  Bo-Cheol Jeong

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Semiconductor devices are provided including a first fin-shaped pattern having first and second sidewalls facing one another and a field insulating film contacting at least a portion of the first fin-shaped pattern. The first fin-shaped pattern includes a lower portion of the first fin-shaped pattern contacting the field insulating film; an upper portion of the first fin-shaped pattern not contacting the field insulating film; a first boundary between the lower portion of the first fin-shaped pattern and the upper portion of the first fin-shaped pattern; and a first fin center line perpendicular to the first boundary and meeting the top of the upper portion of the first fin-shaped pattern. The first sidewall of the upper portion of the first fin-shaped pattern and the second sidewall of the upper portion of the first fin-shaped pattern are asymmetric with respect to the first fin center line.

公开(公告)号：US10522539B2

公开(公告)日：2019-12-31

申请号：US16211851

申请日：2018-12-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Sug-Hyun Sung

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

公开(公告)号：US10276570B2

公开(公告)日：2019-04-30

申请号：US15944956

申请日：2018-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Hyung-Jong Lee ,  Sung-Min Kim ,  Chong-Kwang Chang

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/485 ,  H01L23/532 ,  H01L23/528

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

公开(公告)号：US09941281B2

公开(公告)日：2018-04-10

申请号：US15409033

申请日：2017-01-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Gun You ,  Hyung-Jong Lee ,  Sung-Min Kim ,  Chong-Kwang Chang

IPC: H01L27/088 ,  H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L23/485 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L29/0649

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

公开(公告)号：US09859398B2

公开(公告)日：2018-01-02

申请号：US15438868

申请日：2017-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Se-Wan Park ,  Seung-Woo Do ,  In-Won Park ,  Sug-Hyun Sung

IPC: H01L29/66 ,  H01L21/306 ,  H01L29/417 ,  H01L21/762 ,  H01L21/308 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.