公开(公告)号：US09865495B2

公开(公告)日：2018-01-09

申请号：US15220094

申请日：2016-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Gi-Gwan Park ,  Jung-Gun You ,  Hyung-Dong Kim ,  Sug-Hyun Sung ,  Myung-Yoon Um

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/11

CPC classification number: H01L21/76229 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7853

Abstract: A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench.

公开(公告)号：US10038093B2

公开(公告)日：2018-07-31

申请号：US15223332

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7854

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US20150132908A1

公开(公告)日：2015-05-14

申请号：US14294429

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Shi Ii Quan ,  Sug-Hyun Sung

IPC: H01L29/66 ,  H01L21/02

CPC classification number: H01L29/66545 ,  H01L29/66795

Abstract: A semiconductor device and method of fabricating the device, includes forming a fin-type active pattern that projects above a field insulating layer and forming a dummy gate structure that includes an epitaxial growth prevention layer to suppress nodule formation.

Abstract translation: 一种制造该器件的半导体器件和方法，包括形成在场绝缘层上方突出的鳍状有源图案，并形成包含外延生长防止层的虚拟栅极结构，以抑制结核形成。

公开(公告)号：US10211204B2

公开(公告)日：2019-02-19

申请号：US15708512

申请日：2017-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Sug-Hyun Sung

IPC: H01L21/8238 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/78

Abstract: Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

公开(公告)号：US20180331220A1

公开(公告)日：2018-11-15

申请号：US16028918

申请日：2018-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun YOU ,  Gi-gwan PARK ,  Ki-il KIM

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L29/7843 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7854

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.

公开(公告)号：US09711504B2

公开(公告)日：2017-07-18

申请号：US15155744

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Ki-Il Kim ,  Gi-Gwan Park ,  Sug-Hyun Sung ,  Myung-Yoon Um

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part. The first fin pattern includes a first sidewall and a second sidewall opposite each other. The first sidewall is concave along the lower part of the first fin pattern. The second sidewall is tilted along the lower part of the first fin pattern. The field insulating layer surrounds the lower part of the first fin pattern. The gate electrode surrounds the upper part of the first fin pattern.

公开(公告)号：US09887194B2

公开(公告)日：2018-02-06

申请号：US14989876

申请日：2016-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun You ,  Sug-Hyun Sung ,  Se-Wan Park

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8234

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/42376

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a fin which comprises long sides and a first short side, a first trench which is immediately adjacent the first short side of the fin and has a first depth, a second trench which is immediately adjacent the first trench and has a second depth greater than the first depth, a first protrusion structure which protrudes from a bottom of the first trench and extends side by side with the first short side, and a gate which is formed on the first protrusion structure to extend side by side with the first short side.

公开(公告)号：US20170133264A1

公开(公告)日：2017-05-11

申请号：US15220094

申请日：2016-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il Kim ,  Gi-Gwan Park ,  Jung-Gun You ,  Hyung-Dong Kim ,  Sug-Hyun Sung ,  Myung-Yoon Um

IPC: H01L21/762 ,  H01L27/11 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76229 ,  H01L27/1104 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7853

Abstract: A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a substrate, removing the dummy mask pattern and etching the substrate using the real mask pattern as a mask to form a first trench, a second trench, and a fin-type pattern defined by the first trench and the second trench. The second trench contacting the fin-type pattern comprises a smooth pattern which is convex and positioned between a bottom surface and a side surface of the second trench, a first concave portion which is positioned between the side surface of the second trench and the smooth pattern, and a second concave portion which is positioned between the convex portion and the bottom surface of the second trench.

公开(公告)号：US20170047326A1

公开(公告)日：2017-02-16

申请号：US15155744

申请日：2016-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Gun YOU ,  Ki-Il Kim ,  Gi-Gwan Park ,  Sug-Hyun Sung ,  Myung-Yoon Um

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/7854

Abstract: A semiconductor device includes a substrate including a first trench, a first fin pattern on the substrate that is defined by the first trench, a gate electrode on the substrate, and a field insulating layer on the substrate. The first fin pattern includes an upper part on a lower part. The first fin pattern includes a first sidewall and a second sidewall opposite each other. The first sidewall is concave along the lower part of the first fin pattern. The second sidewall is tilted along the lower part of the first fin pattern. The field insulating layer surrounds the lower part of the first fin pattern. The gate electrode surrounds the upper part of the first fin pattern.

Abstract translation: 半导体器件包括：衬底，包括第一沟槽，由第一沟槽限定的衬底上的第一鳍图案，衬底上的栅电极和衬底上的场绝缘层。 第一鳍状图案包括下部的上部。 第一翅片图案包括彼此相对的第一侧壁和第二侧壁。 第一侧壁沿着第一鳍片图案的下部是凹形的。 第二侧壁沿着第一翅片图案的下部倾斜。 场绝缘层围绕第一鳍片图案的下部。 栅极电极围绕第一鳍片图案的上部。

公开(公告)号：US10707348B2

公开(公告)日：2020-07-07

申请号：US16587227

申请日：2019-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sug-Hyun Sung ,  Jung-gun You ,  Gi-gwan Park ,  Ki-il Kim

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/06 ,  H01L27/092 ,  H01L29/66 ,  H01L21/762

Abstract: An integrated circuit device includes a fin-type active area protruding from a substrate; a plurality of liners sequentially covering lower side walls of the fin-type active area; a device isolation layer covering the lower side walls of the fin-type active area with the plurality of liners between the device isolation layer and the fin-type active area; and a gate insulating layer extending to cover a channel region of the fin-type active area, the plurality of liners, and the device isolation layer, and including protrusions located on portions of the gate insulating layer which cover the plurality of liners.