公开(公告)号：US10789127B2

公开(公告)日：2020-09-29

申请号：US16057855

申请日：2018-08-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunyeong Yu ,  Bohwan Jun ,  Kijun Lee ,  Junjin Kong ,  Hong-Rak Son

IPC: G06F11/10 ,  H03M13/11 ,  H03M13/00 ,  H03M13/39

Abstract: A method of operating a memory controller that performs decoding by using a parity check matrix corresponding to a convolution-type low density parity check (LDPC) code includes receiving a codeword from at least one memory device, the codeword including a first sub-codeword and a second sub-codeword; decoding a first sub-codeword into first data by using first sliding windows in a first direction, set based on a first sub-matrix included in the parity check matrix and associated with the first sub-codeword; and decoding a second sub-codeword into second data by using second sliding windows in a second direction, set based on a second sub-matrix included in the parity check matrix and associated with the second sub-codeword.

公开(公告)号：US09818485B2

公开(公告)日：2017-11-14

申请号：US15178135

申请日：2016-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  Jongha Kim ,  Junjin Kong

IPC: G11C16/16 ,  G06F12/02 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/16 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/0466 ,  G11C16/3445

Abstract: An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.

公开(公告)号：US09785379B2

公开(公告)日：2017-10-10

申请号：US14616153

申请日：2015-02-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Chu Oh ,  JongHa Kim ,  Junjin Kong ,  Hong Rak Son

IPC: G06F3/06 ,  G06F12/00

CPC classification number: G06F3/0656 ,  G06F3/061 ,  G06F3/0679 ,  G06F12/00 ,  G06F12/0246

Abstract: An operating method of a nonvolatile memory device which includes receiving a plurality of sub-page data and a write command from an external device; performing a pre-main program operation such that at least one of the plurality of sub-page data is stored in the second plurality of memory cells included in the main region; performing a buffered program operation such that other received sub-page data is stored in the first plurality of memory cells included in the buffer region; and performing a re-main program operation such that the received sub-page data subjected to the buffered program operation at the buffer region is stored in the second plurality of memory cells subjected to the pre-main program operation.

公开(公告)号：US09336887B2

公开(公告)日：2016-05-10

申请号：US14512965

申请日：2014-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changkyu Seol ,  Euncheol Kim ,  Junjin Kong ,  Hong Rak Son

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  H01L27/115 ,  G11C11/56 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3427 ,  G11C2211/5641 ,  H01L27/11578

Abstract: A nonvolatile memory device includes a memory cell array having multiple memory blocks. Each memory block includes memory cells arranged at intersections of multiple word lines and multiple bit lines. At least one word line of the multiple word lines is included in an upper word line group and at least one other word line of the multiple word lines is included in a lower word line group. The number of data bits stored in memory cells connected to the at least one word line included in the upper word line group is different from the number of data bits stored in memory cells connected to the at least one other word line included in the lower word line group.

Abstract translation: 非易失性存储器件包括具有多个存储块的存储单元阵列。 每个存储块包括布置在多个字线和多个位线的交点处的存储器单元。 多个字线的至少一个字线被包括在上部字线组中，并且多个字线的至少一个其它字线被包括在下部字线组中。 连接到包括在上部字线组中的至少一个字线的存储器单元中存储的数据位的数量不同于存储在连接到包含在下一个字中的至少一个其它字线的存储器单元中的数据位的数量 线组。

公开(公告)号：US08996964B2

公开(公告)日：2015-03-31

申请号：US13786509

申请日：2013-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seonghyeog Choi ,  Junjin Kong ,  Hong Rak Son ,  Pilsang Yoon

IPC: H03M13/00 ,  H03M13/37 ,  H03M13/45

CPC classification number: H03M13/3784 ,  H03M13/3707 ,  H03M13/45

Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.

Abstract translation: 存储装置包括包括多个存储器单元的非易失性存储器件，以及错误校正电路，被配置为从非易失性存储器件接收主数据和辅助数据，并对主数据进行硬判决解码操作，并进一步被配置为执行 基于次要数据对主数据进行软判决解码操作。 在硬判决读取操作中从多个存储器单元中读取主数据，并且从主数据中从被编程到特定状态的存储器单元读取次数据。

公开(公告)号：US08873290B2

公开(公告)日：2014-10-28

申请号：US14225601

申请日：2014-03-26

Applicant: SAMSUNG Electronics Co., Ltd

Inventor： Kyoung Lae Cho ,  Heeseok Eun ,  Junjin Kong

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459

Abstract: A method of programming a non-volatile memory device including a plurality of strings arranged in rows and columns comprises activating all or a part of selection lines in one column at the same time depending upon data to be programmed, driving a bit line corresponding to the one column with a bit line program voltage, and repeating the activating and the driving until bit lines corresponding to the columns are all driven.

Abstract translation: 一种编程包括以行和列排列的多个串的非易失性存储器件的方法包括根据要编程的数据同时激活一列中的一列中的全部或一部分选择线，驱动对应于 具有位线编程电压的一列，并重复激活和驱动，直到与列相对应的位线都被驱动。

公开(公告)号：US08839080B2

公开(公告)日：2014-09-16

申请号：US14089361

申请日：2013-11-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong June Kim ,  Junjin Kong ,  KyoungLae Cho

IPC: H03M13/00 ,  G11C16/34 ,  G06F11/10 ,  G11C11/56

CPC classification number: G06F11/1072 ,  G06F11/1048 ,  G11C11/5642 ,  G11C16/3404 ,  G11C16/349

Abstract: Methods of operating nonvolatile memory devices include testing strings of nonvolatile memory cells in the memory device to identify at least one weak string therein having a higher probability of yielding erroneous read data error relative to other strings. An identity of the at least one weak string may be stored as weak column information, which may be used to facilitate error detection and correction operations. In particular, an error correction operation may be performed on bits of data read from the strings using an algorithm that modifies a weighting of the reliability of one or more data bits in the bits of data based on the weak column information. More specifically, an algorithm may be used that interprets a bit of data read from the at least one weak string as having a relatively reduced reliability relative to other ones of the data bits.

Abstract translation: 操作非易失性存储器件的方法包括测试存储器件中的非易失性存储器单元的串，以识别其中至少一个弱串，其中相对于其它串产生错误的读数据误差的概率较高。 至少一个弱字符串的身份可以存储为弱列信息，其可以用于促进错误检测和校正操作。 特别地，可以使用基于弱列信息修改数据位中的一个或多个数据位的可靠性的加权的算法来对从字符串读取的数据的位进行纠错操作。 更具体地，可以使用解释从至少一个弱串读取的数据位相对于其他数据位相对降低的可靠性的算法。