公开(公告)号：US09741764B1

公开(公告)日：2017-08-22

申请号：US15257609

申请日：2016-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Masayuki Terai ,  Gwan-hyeob Koh ,  Dae-hwan Kang

IPC: H01L27/00 ,  H01L27/24 ,  H01L45/00 ,  H01L27/11582 ,  H01L27/10 ,  G11C13/00 ,  H01L27/06

CPC classification number: H01L27/2427 ,  G11C11/1659 ,  G11C13/0002 ,  G11C13/003 ,  G11C2213/17 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/79 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/11582 ,  H01L27/2454 ,  H01L27/2481 ,  H01L27/249 ,  H01L43/08 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first conductive line and extending in a second direction crossing the first direction, a third conductive line over the second conductive line and extending in the first direction, a first memory cell at an intersection of the first conductive line and the second conductive line and including a first selection element layer and a first variable resistance layer, and a second memory cell at an intersection of the second conductive line and the third conductive line and including a second selection element layer and a second variable resistance layer. A first height of the first selection element layer in a third direction perpendicular to the first and second directions is different than a second height of the second selection element layer in the third direction.

公开(公告)号：US09184218B2

公开(公告)日：2015-11-10

申请号：US14506005

申请日：2014-10-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lijie Zhang ,  Young-Bae Kim ,  Youn-Seon Kang ,  In-Gyu Baek ,  Masayuki Terai

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L27/2454 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

Abstract: A semiconductor memory device includes pillars extending upright on a substrate in a direction perpendicular to the substrate, a stack disposed on the substrate and constituted by a first interlayer insulating layer, a first conductive layer, a second interlayer insulating layer, and a second conductive layer, a variable resistance layer interposed between the pillars and the first conductive layer, and an insulating layer interposed between the first pillars and the second conductive layer.

Abstract translation: 半导体存储器件包括在垂直于衬底的方向上在衬底上直立延伸的柱，设置在衬底上并由第一层间绝缘层，第一导电层，第二层间绝缘层和第二导电层 插入在所述柱和所述第一导电层之间的可变电阻层以及插在所述第一柱和所述第二导电层之间的绝缘层。