SEMICONDUCTOR MEMORY DEVICE
    22.
    发明公开

    公开(公告)号:US20240196593A1

    公开(公告)日:2024-06-13

    申请号:US18225798

    申请日:2023-07-25

    CPC classification number: H10B12/315 H10B12/05

    Abstract: A semiconductor memory device includes a bit line on a substrate and extending in a first direction parallel to a bottom surface of the substrate, a first active pattern on the bit line, a first word line intersecting the first active pattern in a second direction which is parallel to the bottom surface of the substrate and intersects the first direction, and a first conductive pattern on the first active pattern. The first word line includes a first side surface facing the first direction. The first active pattern includes a first portion between the first word line and the first conductive pattern, a second portion between the first word line and the bit line, and a third portion extending on the first side surface of the first word line to connect the first portion to the second portion of the first active pattern.

    DRIVING ASSEMBLY AND MOTION ASSISTANCE DEVICE INCLUDING THE SAME

    公开(公告)号:US20230190566A1

    公开(公告)日:2023-06-22

    申请号:US18110460

    申请日:2023-02-16

    Abstract: A wearable device may include a proximal support configured to support a proximal part (e.g., waist) of a user, a distal support configured to support a distal part (e.g., thigh) of the user, a driving assembly which is connected to the proximal support and configured to generate power, and a driving frame configured to transmit the force from the driving assembly to the distal support. The driving assembly may include a housing which is connected to the proximal support, an actuator including a stator which is fixed to the housing and has a ring shape and a rotor which is located inside the stator and rotatable relative to the stator, a speed reducer which is inserted inside the rotor and includes an input end which is connected to an output end of the actuator, and a supporting part configured to support the speed reducer and connected detachably to the housing.

    SEMICONDUCTOR MEMORY DEVICE
    25.
    发明申请

    公开(公告)号:US20220406791A1

    公开(公告)日:2022-12-22

    申请号:US17729024

    申请日:2022-04-26

    Abstract: Provided is a semiconductor memory device comprising a device isolation pattern in a substrate and defining first and second active sections spaced apart from each other, wherein a center of the first active section is adjacent to an end of the second active section, a bit line that crosses over the center of the first active section, a bit-line contact between the bit line and the first active section, and a first storage node pad on the end of the second active section. The first storage node pad includes a first pad sidewall and a second pad sidewall. The first pad sidewall is adjacent to the bit-line contact. The second pad sidewall is opposite to the first pad sidewall. When viewed in plan, the second pad sidewall is convex in a direction away from the bit-line contact.

    SEMICONDUCTOR DEVICE INCLUDING STORAGE NODE ELECTRODE INCLUDING STEP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

    公开(公告)号:US20220246621A1

    公开(公告)日:2022-08-04

    申请号:US17725806

    申请日:2022-04-21

    Abstract: A semiconductor device may include a bottom sub-electrode on a substrate, a top sub-electrode on the bottom sub-electrode, a dielectric layer covering the bottom and top sub-electrodes, and a plate electrode on the dielectric layer. The top sub-electrode may include a step extending from a side surface thereof, which is adjacent to the bottom sub-electrode, to an inner portion of the top sub-electrode. The top sub-electrode may include a lower portion at a level that is lower than the step and an upper portion at a level which is higher than the step. A maximum width of the lower portion may be narrower than a minimum width of the upper portion. The maximum width of the lower portion may be narrower than a width of a top end of the bottom sub-electrode. The bottom sub-electrode may include a recess in a region adjacent to the top sub-electrode.

    SEMICONDUCTOR DEVICES
    27.
    发明申请

    公开(公告)号:US20220149048A1

    公开(公告)日:2022-05-12

    申请号:US17357139

    申请日:2021-06-24

    Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure covering a lower sidewall of the bit line structure, a contact plug structure on the active pattern and adjacent to the bit line structure, and a capacitor on the contact plug structure. The lower spacer structure includes first and second lower spacers that are sequentially stacked from the lower sidewall of the bit line structure in a horizontal direction that is substantially parallel to an upper surface of the substrate, the first lower spacer includes an oxide, and contacts the lower sidewall of the bit line structure, but does not contact the contact plug structure, and the second lower spacer includes a material different from any of the materials of the first lower spacer.

    INTER-CELL INTERFERENCE MITIGATION METHOD IN DYNAMIC TIME DIVISION DUPLEX ENVIRONMENT, AND ELECTRONIC DEVICE FOR SAME

    公开(公告)号:US20210399821A1

    公开(公告)日:2021-12-23

    申请号:US17283927

    申请日:2019-09-19

    Abstract: The present invention provides an electronic device for mitigating inter-cell interference in a dynamic TDD environment, the electronic device including: at least one antenna array including antenna elements; and a processor configured to use the antenna array and form a plurality of reception beams having mutually different directions, wherein at least one processor may enable: a first beam pair link to be formed with a first transmission beam emitted from a first base station by using a first reception beam having a first direction; information about a first TDD pattern indicating a TDD sequence set in a serving cell formed by the first base station and information about a second TDD pattern indicating a TDD sequence set in an adjacent cell adjacent to a serving cell formed by a second base station to be acquired; a first portion of the first TDD pattern to be selected on the basis of the information about the first TDD pattern and the information about the second TDD pattern; the detection of whether interference has occurred in the first portion; and a second beam pair link to be formed with one among transmission beams emitted from the second base station by using a second reception beam having a second direction different from the first direction, when the interference is determined to have occurred.

    ELECTRONIC DEVICE AND METHOD FOR DETERMINING UPLINK OPERATION IN WIRELESS COMMUNICATION SYSTEM

    公开(公告)号:US20210392649A1

    公开(公告)日:2021-12-16

    申请号:US17285528

    申请日:2019-11-15

    Abstract: An electronic device, according to various embodiments of the present invention, may comprise: a first communication circuit configured to provide first wireless communication using a first frequency band; a second communication circuit configured to provide second wireless communication using a second frequency band; a processor operatively connected with the first communication circuit and the second communication circuit; and a memory operatively connected with the processor, and configured to store information about the first frequency band and the second frequency band, wherein the memory can store instructions configured to, when executed, enable the processor to communicate with a first base station using the first communication circuit, to receive a first signal from the first base station, and to receive a second signal from a second base station using the second communication circuit on the basis of information on the frequency band while communicating with the first base station, and to select one of a single uplink operation or a dual uplink operation on the basis of information obtained or measured in response to receiving the first signal or the second signal.

    MODULE COMPRISING ANTENNA AND RF ELEMENT, AND BASE STATION INCLUDING SAME

    公开(公告)号:US20210344120A1

    公开(公告)日:2021-11-04

    申请号:US17373000

    申请日:2021-07-12

    Abstract: A communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT) are provided. The disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. According to the disclosure, an antenna module includes a first substrate layer on which at least one substrate is stacked; an antenna coupled to an upper end surface of the first substrate layer; a second substrate layer having an upper end surface coupled to a lower end surface of the first substrate layer and on which at least one substrate is stacked; and a radio frequency (RF) element coupled to a lower end surface of the second substrate layer.

Patent Agency Ranking