公开(公告)号：US11233146B2

公开(公告)日：2022-01-25

申请号：US16828049

申请日：2020-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hyun Song ,  Chang Woo Sohn ,  Young Chai Jung ,  Sa Hwan Hong

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L29/40

Abstract: A vertical field-effect transistor (VFET) device and a method of manufacturing the same are provided. The VFET device includes: a fin structure formed on a substrate; a gate structure including a gate dielectric layer formed on an upper portion of a sidewall of the fin structure, and a conductor layer formed on a lower portion of the gate dielectric layer; a top source/drain (S/D) region formed above the fin structure and the gate structure; a bottom S/D region formed below the fin structure and the gate structure; a top spacer formed on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer formed between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

公开(公告)号：US11145757B2

公开(公告)日：2021-10-12

申请号：US16713054

申请日：2019-12-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Chai Jung ,  Seon Bae Kim ,  Seung Hyun Song

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/085

Abstract: Integrated circuit devices and methods of forming the same are provided. Integrated circuit devices may include a vertical field-effect transistor (VFET) that includes a bottom source/drain region in a substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, and a gate structure on a side of the channel region. The channel region may have a cross-shaped upper surface.

公开(公告)号：US20210111271A1

公开(公告)日：2021-04-15

申请号：US16824196

申请日：2020-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Bae Kim ,  Seung Hyun Song ,  Young Chai Jung

IPC: H01L29/66 ,  H01L21/308 ,  H01L29/06

Abstract: A method for manufacturing a fin structure of a vertical field effect transistor (VFET) includes: (a) patterning a lower layer and an upper layer, deposited on the lower layer, to form two patterns extended in two perpendicular directions, respectively; (b) forming a first spacer and a second spacer side by side in the two patterns along sidewalls of the lower layer and the upper layer exposed through the patterning; (c) removing the first spacer, the second spacer and the upper layer above a level of a top surface of the lower layer, and the first spacer below the level of the top surface of the lower layer and exposed through the two patterns in the plan view; (d) removing the lower layer, the upper layer, and the second spacer remaining on the substrate after operation (c); and (e) etching the substrate downward except a portion thereof below the first spacer remaining on the substrate after operation (d), and removing the remaining first spacer, thereby to obtain the fin structure.

公开(公告)号：US10950604B2

公开(公告)日：2021-03-16

申请号：US16908829

申请日：2020-06-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung Hyun Song ,  Yoon Suk Kim ,  Kyu Baik Chang ,  Ui Hui Kwon ,  Yo Han Kim ,  Jong Choi Kim ,  Chang Wook Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L27/02 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/8234

Abstract: A semiconductor device includes a fin-type pattern extending in a first direction, a device isolation film surrounding the fin-type pattern, while exposing an upper portion of the fin-type pattern, a gate electrode extending on the device isolation film and the fin-type pattern in a second direction intersecting the first direction, a gate isolation film isolating the gate electrode in the second direction, and including a first material and on the device isolation film, an interlayer insulating film filling a side surface of the fin-type pattern and including a second material different from the first material.

公开(公告)号：US10164017B2

公开(公告)日：2018-12-25

申请号：US15887773

申请日：2018-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro Sasaki ,  Bong Soo Kim ,  Tae Gon Kim ,  Yoshiya Moriyama ,  Seung Hyun Song ,  Alexander Schmidt ,  Abraham Yoo ,  Heung Soon Lee ,  Kyung In Choi

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/223 ,  H01L21/265

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.

公开(公告)号：US09911809B2

公开(公告)日：2018-03-06

申请号：US15424081

申请日：2017-02-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yuichiro Sasaki ,  Bong Soo Kim ,  Tae Gon Kim ,  Yoshiya Moriyama ,  Seung Hyun Song ,  Alexander Schmidt ,  Abraham Yoo ,  Heung Soon Lee ,  Kyung In Choi

IPC: H01L29/10 ,  H01L29/78 ,  H01L27/092 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238

CPC classification number: H01L29/1083 ,  H01L21/2236 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed region between the protruding regions. Gate structures overlapping the protruding regions are disposed. An epitaxial layer is disposed in the recessed region to have a height greater than a width. An impurity region is disposed in the fin active region, surrounds side walls and a bottom of the recessed region, has the same conductivity type as a conductivity type of the epitaxial layer, and includes a majority impurity that is different from a majority impurity included in at least a portion of the epitaxial layer.