公开(公告)号：US12132044B2

公开(公告)日：2024-10-29

申请号：US16734786

申请日：2020-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sung Min Kim ,  Dae Won Ha

IPC: H01L27/06 ,  H01L21/768 ,  H01L21/822 ,  H01L23/528 ,  H01L27/088 ,  H01L27/146 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0688 ,  H01L21/76898 ,  H01L21/8221 ,  H01L23/5283 ,  H01L27/088 ,  H01L27/14636 ,  H01L29/4175 ,  H01L29/78391 ,  H01L29/7843 ,  H01L2225/06541

Abstract: A semiconductor device including: a lower semiconductor substrate; an upper semiconductor substrate overlapping the lower semiconductor substrate, the upper semiconductor substrate including a first surface and a second surface opposite to the first surface; an upper gate structure on the first surface of the upper semiconductor substrate; a first interlayer insulation film which covers the upper gate structure, wherein the first interlayer insulation film is between the lower semiconductor substrate and the upper semiconductor substrate; and an upper contact connected to the lower semiconductor substrate, wherein the upper contact is on a side surface of the upper gate structure, wherein the upper contact includes a first portion penetrating the upper semiconductor substrate, and a second portion having a side surface adjacent to the side surface of the upper gate structure, and a width of the first portion decreases toward the second surface.

公开(公告)号：US12009346B2

公开(公告)日：2024-06-11

申请号：US18328389

申请日：2023-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Dae Won Ha

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/08 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80894 ,  H01L2225/06524 ,  H01L2225/06544 ,  H01L2225/06593

Abstract: A device includes a lower semiconductor substrate, a lower gate structure on the lower semiconductor substrate, the lower gate structure comprises a lower gate electrode, a lower interlayer insulating film on the lower semiconductor substrate, an upper semiconductor substrate on the lower interlayer insulating film, an upper gate structure on the upper semiconductor substrate, and an upper interlayer insulating film on the lower interlayer insulating film, the upper interlayer insulating film covers sidewalls of the upper semiconductor substrate The upper gate structure comprises an upper gate electrode extending in a first direction and gate spacers along sidewalls of the upper gate electrode. The upper gate electrode comprises long sidewalls extending in the first direction and short sidewalls in a second direction The gate spacers are on the long sidewalls of the upper gate electrode and are not disposed on the short sidewalls of the upper gate electrode.

公开(公告)号：US11195952B2

公开(公告)日：2021-12-07

申请号：US16402292

申请日：2019-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Hyo Jin Kim ,  Dae Won Ha

IPC: H01L29/78 ,  H01L21/762

Abstract: Semiconductor devices are provided. A semiconductor device includes a fin structure including a stress structure and a semiconductor region that are sequentially stacked on a substrate. The semiconductor device includes a field insulation layer on a portion of the fin structure. The semiconductor device includes a gate electrode on the fin structure. Moreover, the stress structure includes an oxide.

公开(公告)号：US09755049B2

公开(公告)日：2017-09-05

申请号：US15000425

申请日：2016-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunhom Steve Paak ,  Sung Min Kim

IPC: H01L29/66 ,  H01L21/308 ,  H01L27/11524 ,  H01L27/11536 ,  H01L21/762 ,  H01L27/11

CPC classification number: H01L29/6656 ,  H01L21/3086 ,  H01L21/76232 ,  H01L27/1104 ,  H01L27/11524 ,  H01L27/11536

Abstract: Methods for fabricating semiconductor devices are provided including sequentially stacking hardmask layers, a first sacrificial layer, and a second sacrificial layer on a substrate, forming first mandrels on the first sacrificial layer by etching the second sacrificial layer, forming first spacers on side walls of the first mandrels, forming a photoresist pattern disposed outside a region from which the first mandrels have been removed, forming second and third mandrels by etching the first sacrificial layer using the first spacers and the photoresist pattern as respective etching masks, forming second and third spacers on side walls of the second and third mandrels, forming first and second active patterns respectively having first and second pitches by etching the hardmask layer and at least a portion of the substrate, and forming a device isolation layer so that upper portions of the first and second active patterns protrude therefrom.

公开(公告)号：US12266656B2

公开(公告)日：2025-04-01

申请号：US17210751

申请日：2021-03-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Mun Hyeon Kim ,  Sung Min Kim ,  Dae Won Ha

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786

Abstract: A semiconductor device includes a substrate with first and second regions separated from each other, a laminate structure including at least one sacrificial layer and at least one active layer alternately stacked on the substrate, a first isolation insulating layer on the laminate structure on the first region, a second isolation insulating layer on the laminate structure on the second region, the second isolation insulating layer having a same thickness as the first isolation insulating layer, a first upper active pattern spaced apart from the first isolation insulating layer, a first gate electrode surrounding at least a portion of the first upper active pattern, a second upper active pattern spaced apart from the second isolation insulating layer, and a second gate electrode surrounding at least a portion of the second upper active pattern, wherein top surfaces of the first and second isolation insulating layers are at different heights.

公开(公告)号：US12243754B2

公开(公告)日：2025-03-04

申请号：US17517304

申请日：2021-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Do Young Choi ,  Sung Min Kim ,  Cheol Kim ,  Hyo Jin Kim ,  Dae Won Ha ,  Dong Woo Han

IPC: H01L21/3213 ,  H01L21/308 ,  H01L27/088 ,  H01L27/092

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

公开(公告)号：US11764299B2

公开(公告)日：2023-09-19

申请号：US17560353

申请日：2021-12-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Hom Paak ,  Sung Min Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L23/485

CPC classification number: H01L29/7845 ,  H01L23/485 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41791

Abstract: A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape.

公开(公告)号：US11211490B2

公开(公告)日：2021-12-28

申请号：US16794326

申请日：2020-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun Hom Paak ,  Sung Min Kim

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L23/485

Abstract: A semiconductor device includes an active fin extending in a first direction on a substrate, a gate electrode intersecting the active fin and extending in a second direction, source/drain regions disposed on the active fin on both sides of the gate electrode, and a contact plug disposed on the source/drain regions. The contact plug has at least one side extending in the second direction which has a step portion having a step shape.

公开(公告)号：US11063065B2

公开(公告)日：2021-07-13

申请号：US16454532

申请日：2019-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Guk Il An ,  Keun Hwi Cho ,  Sung Min Kim ,  Yoon Moon Park

IPC: H01L27/1159 ,  H01L27/11592

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first interfacial layer disposed on the substrate in the first region and having a first thickness; a second interfacial layer disposed on the substrate in the second region, wherein the second interfacial layer includes a second thickness that is smaller than the first thickness; a first gate insulating layer disposed on the first interfacial layer and including a first ferroelectric material layer; a second gate insulating layer disposed on the second interfacial layer; a first gate electrode disposed on the first gate insulating layer; and a second gate electrode disposed on the second gate insulating layer.

公开(公告)号：US10910374B2

公开(公告)日：2021-02-02

申请号：US16926360

申请日：2020-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung Min Kim ,  Dong Won Kim

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L21/8234 ,  H01L21/768 ,  H01L29/66

Abstract: A semiconductor device is provided, which includes a first and second multichannel active patterns spaced apart from one another and extending in a first direction. The semiconductor device also includes first and second gate structures on the first and second multichannel active patterns, extending in a second direction and including first and second gate insulating films, respectively. Sidewalls of the first multichannel active pattern include first portions in contact with the first gate insulating film, second portions not in contact with the first gate insulating film, third portions in contact with the second gate insulating film, and fourth portions not in contact with the second gate insulating film. Additionally, a height of the first portions of the first multichannel active pattern is greater than a height of the third portions of the first multichannel active pattern.