公开(公告)号：US11984170B2

公开(公告)日：2024-05-14

申请号：US18160620

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Chiweon Yoon

IPC: G11C16/32 ,  G11C16/04 ,  H01L25/065

CPC classification number: G11C16/32 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06506

Abstract: A nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.

公开(公告)号：US11502687B2

公开(公告)日：2022-11-15

申请号：US17389148

申请日：2021-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tongsung Kim ,  Youngmin Jo ,  Jungjune Park ,  Jindo Byun ,  Dongho Shin ,  Jeongdon Ihm

IPC: H03K19/00 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/10 ,  H03K19/08

Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.

公开(公告)号：US11336266B2

公开(公告)日：2022-05-17

申请号：US17222033

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongho Shin ,  Kyungtae Kang ,  Junha Lee ,  Tongsung Kim ,  Jangwoo Lee ,  Jeongdon Ihm ,  Byunghoon Jeong

IPC: H03K3/017 ,  H03K19/21 ,  H03K5/24

Abstract: A method of operating a system including a parameter monitoring circuit and a host, includes generating a first parameter applying a first code to a current parameter, wherein a first offset is applied to the first code; generating a first comparison result by comparing the first parameter with a reference parameter value; generating a second parameter applying a second code to the current parameter, wherein a second offset is applied to the second code; generating a second comparison result by comparing the second parameter with the reference parameter value; detecting an error in the current parameter, based on the first comparison result and the second comparison result; and providing a signal based on the error to the host.

公开(公告)号：US11163453B2

公开(公告)日：2021-11-02

申请号：US17027978

申请日：2020-09-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngmin Jo ,  Daeseok Byeon ,  Tongsung Kim

IPC: G06F3/06 ,  G06N3/08 ,  G06F12/02

Abstract: A memory device comprises a smart buffer, and a memory area divided into a first memory area and a second memory area, wherein the smart buffer comprises a priority setting unit configured to receive a sensing data and a corresponding weight from a controller, determine a priority of the sensing data based on the weight, and classify the sensing data as one of first priority sensing data and second priority sensing data, and a channel controller configured to allocate at least one channel selected from among a plurality of channels to a first channel group, allocate at least another channel selected from among the plurality of channels to a second channel group, assign the first channel group to process the first priority sensing data in relation to the first memory area, and assign the second channel group to process the second priority sensing data in relation to the second memory area, wherein a number of data input/output (I/O) pins connected to the first channel group is greater than a number of data I/O pins connected to the second channel group, wherein the memory area includes at least one memory chip, wherein the at least one memory chip includes a first chip having a first metal pad and a cell region and a second chip having a second metal pad and a peripheral circuit region, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.