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公开(公告)号：US11037992B2
公开(公告)日：2021-06-15
申请号：US16567094
申请日：2019-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jeonghee Park , Dongho Ahn , Changyup Park , Zhe Wu
Abstract: A variable resistance memory device including insulating patterns sequentially stacked on a substrate; first conductive lines between adjacent ones of the insulating patterns and spaced apart from each other in a first direction; a second conductive line between the first conductive lines and penetrating the insulating patterns in a third direction perpendicular to a top surface of the substrate; a phase-change pattern between the second conductive line and each of the first conductive lines and between the adjacent ones of the insulating patterns to cover a top surface of a first adjacent insulating pattern and a bottom surface of a second adjacent insulating pattern; and a selection element between the phase-change pattern and the second conductive line and between the adjacent ones of the insulating patterns to cover the top surface of the first adjacent insulating pattern and the bottom surface of the second adjacent insulating pattern.
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公开(公告)号：US10403681B2
公开(公告)日：2019-09-03
申请号：US15832958
申请日：2017-12-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Dong-ho Ahn , Zhe Wu , Soon-oh Park , Hideki Horii
Abstract: A memory device is provided. The memory device includes a variable resistance layer. A selection device layer is electrically connected to the variable resistance layer. The selection device layer includes a chalcogenide switching material having a composition according to chemical formula 1 below, [GeASeBTeC](1-U)[X]U (1) where 0.20≤A≤0.40, 0.40≤B≤0.70, 0.05≤C≤0.25, A+B+C=1, 0.0≤U≤0.20, and X is at least one selected from boron (B), carbon (C), nitrogen (N), oxygen (O), phosphorus (P), or sulfur (S).
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公开(公告)号：US10128312B2
公开(公告)日：2018-11-13
申请号：US15485594
申请日：2017-04-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Zhe Wu , Jeong Hee Park , Dong Ho Ahn , Jin Woo Lee , Hee Ju Shin , Ja Bin Lee
Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.
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公开(公告)号：US20180019281A1
公开(公告)日：2018-01-18
申请号：US15454064
申请日：2017-03-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ja bin LEE , Jeonghee Park , Dongho Ahn , Zhe Wu , Heeju Shin , Jinwoo Lee
CPC classification number: H01L27/2427 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/1625
Abstract: A variable resistance memory device may include separate memory cells between separate vertical intersections of first conductive lines extending in a first direction and second conductive lines extending in a second direction intersecting the first direction. A memory cell may include a switching element and a variable resistance structure coupled in series between a first conductive line and a second conductive line. The switching element may include at least one insulative impurity and a chalcogenide material. The variable resistance structure may reversibly switch phases, between a crystalline state and an amorphous state, at a first phase transition temperature, and the switching element may reversibly switch phases, between a crystalline state and an amorphous state, at a second phase transition temperature, where the second phase transition temperature is greater than the first phase transition temperature.
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