公开(公告)号：US11176982B2

公开(公告)日：2021-11-16

申请号：US17039455

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Kim ,  Hee Ju Shin ,  Ung Hwan Pi

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

公开(公告)号：US11339467B2

公开(公告)日：2022-05-24

申请号：US16793096

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Woong Kim ,  Hyeon Woo Seo ,  Hee Ju Shin ,  Se Chung Oh ,  Hyun Cho

IPC: C23C14/34 ,  C23C14/35 ,  H01J37/32 ,  C23C14/08

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

公开(公告)号：US11735241B2

公开(公告)日：2023-08-22

申请号：US17202648

申请日：2021-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hee Ju Shin ,  Sang Hwan Park ,  Se Chung Oh ,  Ki Woong Kim ,  Hyeon Woo Seo

IPC: G11C11/00 ,  G11C11/16 ,  H01F10/32 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H01F10/3286 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetic memory device includes a pinned layer, a free layer, a tunnel barrier layer between the pinned layer and the free layer, a first oxide layer spaced apart from the tunnel barrier layer with the free layer therebetween, and a second oxide layer spaced apart from the free layer with the first oxide layer therebetween. The first oxide layer includes an oxide of a first material and may have a thickness of 0.3 Å to 2.0 Å. The second oxide layer may include an oxide of a second material and may have a thickness of 0.1 Å to 5.0 Å. A first oxygen affinity of the first material may be greater than a second oxygen affinity of the second material.

公开(公告)号：US20210027822A1

公开(公告)日：2021-01-28

申请号：US17039455

申请日：2020-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon KIM ,  Hee Ju Shin ,  Ung Hwan Pi

IPC: G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

公开(公告)号：US11725271B2

公开(公告)日：2023-08-15

申请号：US17721428

申请日：2022-04-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Woong Kim ,  Hyeon Woo Seo ,  Hee Ju Shin ,  Se Chung Oh ,  Hyun Cho

IPC: C23C14/34 ,  C23C14/35 ,  H01J37/32 ,  C23C14/08 ,  H01J37/34

CPC classification number: C23C14/3464 ,  C23C14/08 ,  C23C14/352 ,  H01J37/32082 ,  H01J37/32155 ,  H01J37/32715 ,  H01J37/3417

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

公开(公告)号：US20210010127A1

公开(公告)日：2021-01-14

申请号：US16793096

申请日：2020-02-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Woong Kim ,  Hyeon Woo Seo ,  Hee Ju Shin ,  Se Chung Oh ,  Hyun Cho

IPC: C23C14/34 ,  C23C14/35 ,  C23C14/08 ,  H01J37/32

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

公开(公告)号：US20200082858A1

公开(公告)日：2020-03-12

申请号：US16369869

申请日：2019-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HOON KIM ,  Hee Ju Shin ,  Ung Hwan Pi

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

公开(公告)号：US20220375983A1

公开(公告)日：2022-11-24

申请号：US17573826

申请日：2022-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Kuk Kang ,  Min Ho Jang ,  Hoon Joo Na ,  Hee Ju Shin

IPC: H01L27/146

Abstract: An image sensor is provided. The image sensor includes unit pixels inside the substrate; a pixel separation pattern provided between the unit pixels, inside the substrate; a first inter-wiring insulating film provided on the first surface of the substrate; a pad pattern provided inside the first inter-wiring insulating film; a first connection pattern provided inside the first inter-wiring insulating film, an upper surface of the first connection pattern and an upper surface of the first inter-wiring insulating film being provided along a first common plane; a second inter-wiring insulating film provided on the upper surface of the first inter-wiring insulating film; a second connection pattern provided inside the second inter-wiring insulating film, a lower surface of the second connection pattern and a lower surface of the second inter-wiring insulating film being provided along a second common plane; and a microlens provided on the second surface of the substrate. The first connection pattern is provided in an island shape from a planar viewpoint.

公开(公告)号：US10825497B2

公开(公告)日：2020-11-03

申请号：US16369869

申请日：2019-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Hoon Kim ,  Hee Ju Shin ,  Ung Hwan Pi

IPC: G11C11/00 ,  G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/10 ,  H01L43/08

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

公开(公告)号：US10128312B2

公开(公告)日：2018-11-13

申请号：US15485594

申请日：2017-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Zhe Wu ,  Jeong Hee Park ,  Dong Ho Ahn ,  Jin Woo Lee ,  Hee Ju Shin ,  Ja Bin Lee

IPC: H01L27/24 ,  H01L23/528 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L45/00

Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.