公开(公告)号：US20250017118A1

公开(公告)日：2025-01-09

申请号：US18412778

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Se Chung Oh ,  JeongMok Kim ,  Tanyoung Kim ,  Heeju Shin ,  YoungJun Cho

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20

Abstract: A magnetic memory device includes a reference magnetic pattern and a free magnetic pattern stacked on a substrate, a tunnel barrier pattern between the reference magnetic pattern and the free magnetic pattern, a first non-magnetic pattern on the free magnetic pattern, the free magnetic pattern being between the tunnel barrier pattern and the first non-magnetic pattern, a second non-magnetic pattern on the first non-magnetic pattern, the first non-magnetic pattern being between the free magnetic pattern and the second non-magnetic pattern, a metal pattern between the first non-magnetic pattern and the second non-magnetic pattern, and a conductive layer on a side surface of the first non-magnetic pattern.

公开(公告)号：US12190928B2

公开(公告)日：2025-01-07

申请号：US17970788

申请日：2022-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghyun Kim ,  Sechung Oh ,  Heeju Shin ,  Jaehoon Kim ,  Sanghwan Park ,  Junghwan Park

IPC: G11C11/00 ,  G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive random access memory device includes a pinned layer; a tunnel barrier layer on the pinned layer; a free layer structure on the tunnel barrier layer, the free layer structure including a plurality of magnetic layers and a plurality of metal insertion layers between the magnetic layers; and an upper oxide layer on the free layer structure, wherein each of the metal insertion layers includes a non-magnetic metal material doped with a magnetic material, and the metal insertion layers are spaced apart from each other.

公开(公告)号：US20220130581A1

公开(公告)日：2022-04-28

申请号：US17350157

申请日：2021-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghyun Kim ,  Sechung Oh ,  Naoki Hase ,  Heeju Shin ,  Junghwan Park

IPC: H01F10/32 ,  H01L43/02 ,  H01L27/22

Abstract: A magnetic device includes a fixed layer including a fixed pattern, a free layer, and a tunnel barrier between the fixed layer and the free layer. The fixed pattern includes a first magnetic pattern, a second magnetic pattern, and a hybrid spacer, including a nonmagnetic material layer, between the first magnetic pattern and the second magnetic pattern, the nonmagnetic material including a plurality of magnetic nanoparticles dispersed therein.

公开(公告)号：US20180019281A1

公开(公告)日：2018-01-18

申请号：US15454064

申请日：2017-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ja bin LEE ,  Jeonghee Park ,  Dongho Ahn ,  Zhe Wu ,  Heeju Shin ,  Jinwoo Lee

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1625

Abstract: A variable resistance memory device may include separate memory cells between separate vertical intersections of first conductive lines extending in a first direction and second conductive lines extending in a second direction intersecting the first direction. A memory cell may include a switching element and a variable resistance structure coupled in series between a first conductive line and a second conductive line. The switching element may include at least one insulative impurity and a chalcogenide material. The variable resistance structure may reversibly switch phases, between a crystalline state and an amorphous state, at a first phase transition temperature, and the switching element may reversibly switch phases, between a crystalline state and an amorphous state, at a second phase transition temperature, where the second phase transition temperature is greater than the first phase transition temperature.

公开(公告)号：US12029134B2

公开(公告)日：2024-07-02

申请号：US17402960

申请日：2021-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghwan Park ,  Younghyun Kim ,  Jaehoon Kim ,  Heeju Shin ,  Sechung Oh

IPC: H10N50/85 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/22 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device including a substrate; a lower electrode on the substrate; a magnetic tunnel junction structure on the lower electrode, the magnetic tunnel junction structure including a pinned layer, a tunnel barrier layer, and a free layer which are sequentially stacked; an upper electrode on the magnetic tunnel junction structure; and an oxidation control layer between the free layer and the upper electrode, the oxidation control layer including at least one filter layer and at least one oxide layer, wherein the at least one filter layer includes MoCoFe.

公开(公告)号：US11935677B2

公开(公告)日：2024-03-19

申请号：US17350157

申请日：2021-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younghyun Kim ,  Sechung Oh ,  Naoki Hase ,  Heeju Shin ,  Junghwan Park

IPC: H01F10/32 ,  G11C11/16 ,  H01F1/00 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: H01F10/3254 ,  H01F1/0063 ,  H01F10/3272 ,  H01F10/329 ,  H10B61/22 ,  H10N50/10 ,  H10N50/80 ,  G11C11/161 ,  H10N50/85

Abstract: A magnetic device includes a fixed layer including a fixed pattern, a free layer, and a tunnel barrier between the fixed layer and the free layer. The fixed pattern includes a first magnetic pattern, a second magnetic pattern, and a hybrid spacer, including a nonmagnetic material layer, between the first magnetic pattern and the second magnetic pattern, the nonmagnetic material including a plurality of magnetic nanoparticles dispersed therein.

公开(公告)号：US12262641B2

公开(公告)日：2025-03-25

申请号：US17466246

申请日：2021-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungil Hong ,  Jungmin Lee ,  Younghyun Kim ,  Junghwan Park ,  Heeju Shin ,  Se Chung Oh

IPC: H10N50/10 ,  G11C11/16 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method of fabricating a magnetic memory device comprises forming, on a substrate, a data storage structure including a bottom electrode, a magnetic tunnel junction pattern, and a top electrode, forming a first capping dielectric layer conformally covering lateral and top surfaces of the data storage structure, and forming a second capping dielectric layer on the first capping dielectric layer. The forming the first capping dielectric layer is performed by PECVD in which a first source gas, a first reaction gas, and a first purging gas are supplied. The forming the second capping dielectric layer Is performed by PECVD in which a second source gas, a second reaction gas, and a second purging gas are supplied. The first and second reaction gases are different from each other. The first and second purging gases are different from each other.

公开(公告)号：US11942128B2

公开(公告)日：2024-03-26

申请号：US17576047

申请日：2022-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Whankyun Kim ,  Jeong-Heon Park ,  Heeju Shin ,  Youngjun Cho ,  Joonmyoung Lee ,  Junho Jeong

IPC: G11C11/16 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

CPC classification number: G11C11/161 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: Disclosed is a magnetic memory device including a pinned magnetic pattern and a free magnetic pattern that are sequentially stacked on a substrate, a tunnel barrier pattern between the pinned magnetic pattern and the free magnetic pattern, a top electrode on the free magnetic pattern, and a capping pattern between the free magnetic pattern and the top electrode. The capping pattern includes a lower capping pattern, an upper capping pattern between the lower capping pattern and the top electrode, a first non-magnetic pattern between the lower capping pattern and the upper capping pattern, and a second non-magnetic pattern between the first non-magnetic pattern and the upper capping pattern. Each of the lower capping pattern and the upper capping pattern includes a non-magnetic metal. The first non-magnetic pattern and the second non-magnetic pattern include different metals from each other.

公开(公告)号：US09985204B2

公开(公告)日：2018-05-29

申请号：US15451961

申请日：2017-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwoo Lee ,  Jeonghee Park ,  Dongho Ahn ,  Zhe Wu ,  Heeju Shin ,  Ja bin Lee

IPC: H01L45/00 ,  H01L27/24 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L45/141 ,  H01L43/08 ,  H01L43/10 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/16

Abstract: A semiconductor memory device including first lines and second lines overlapping and intersecting each other, variable resistance memory elements disposed at intersections between the first lines and the second lines, and switching elements disposed between the variable resistance memory elements and the first lines. At least one of the switching elements includes first and second chalcogenide compound layers, and conductive nano-dots disposed between the first and second chalcogenide compound layers.