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    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 有权

    公开(公告)号：US20220059615A1

    公开(公告)日：2022-02-24

    申请号：US17364378

    申请日：2021-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong Sung CHOI ,  Jong Uk Kim ,  Kwang Min Park ,  Zhe Wu ,  Ja Bin Lee ,  Jae Ho Jung

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor memory device includes a first memory cell provided on a substrate, a second memory cell provided on the substrate and spaced apart from the first memory cell, a passivation layer extending along a side surface of the first memory cell and a side surface of the second memory cell, and a gap fill layer covering the passivation layer. Each of the first memory cell and the second memory cell includes a selection pattern having ovonic threshold switching characteristics, and a storage pattern provided on the selection pattern. The passivation layer includes a lower portion filling a space between the selection pattern of the first memory cell and the selection pattern of the second memory cell, and an upper portion extending along a side surface of the storage pattern of each of the first memory cell and the second memory cell.

    Non-volatile memory device
    6.
    发明授权
    Non-volatile memory device 有权

    公开(公告)号：US10128312B2

    公开(公告)日：2018-11-13

    申请号：US15485594

    申请日：2017-04-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Zhe Wu ,  Jeong Hee Park ,  Dong Ho Ahn ,  Jin Woo Lee ,  Hee Ju Shin ,  Ja Bin Lee

    IPC: H01L27/24 ,  H01L23/528 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L45/00

    Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

    Memory device, memory cell and method for programming memory cell
    8.
    发明授权
    Memory device, memory cell and method for programming memory cell 有权

    公开(公告)号：US11152064B2

    公开(公告)日：2021-10-19

    申请号：US16530517

    申请日：2019-08-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Zhe Wu ,  Ja Bin Lee ,  Jin Woo Lee ,  Kyu Bong Jung

    IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

    Abstract: A memory device includes a word line, a bit line intersecting the word line, and a memory cell at an intersection of the word line and the bit line. The memory cell includes a first electrode connected to the word line; a second electrode connected to the bit line; and a selective element layer between the first electrode and the second electrode. The selective element layer includes one of Ge—Se—Te, Ge—Se—Te—As, and Ge—Se—Te—As—Si, and a composition ratio of arsenic (As) component of each of the Ge—Se—Te—As and the Ge—Se—Te—As—Si being greater than 0.01 and less than 0.17.

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