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公开(公告)号：US12046306B2
公开(公告)日：2024-07-23
申请号：US17826434
申请日：2022-05-27
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Ravi Kumar
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/102 , G11C16/26
Abstract: The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.
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公开(公告)号：US20220399066A1
公开(公告)日：2022-12-15
申请号：US17347772
申请日：2021-06-15
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Dengtao Zhao , Anubhav Khandelwal , Ravi Kumar
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.
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23.发明授权公开(公告)号：US11417393B2
公开(公告)日：2022-08-16
申请号：US17142753
申请日：2021-01-06
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Muhammad Masuduzzaman , Ravi Kumar
Abstract: A method for programming a non-volatile memory structure with four-page data, wherein the method comprises, in a first stage, selecting four programmable states of a segment of MLC NAND-type memory cells, programming at least a first of the four programmable states with two pages of a four-page data at a first step voltage level, between programming at least two neighboring programmable states of the four programmable states, increasing the first step voltage level to a second step voltage level for a single program pulse and according to a pre-determined magnitude, and programming a latter of the at least two neighboring programmable states at the first step voltage level.
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公开(公告)号：US20220254416A1
公开(公告)日：2022-08-11
申请号：US17173852
申请日：2021-02-11
Applicant: SanDisk Technologies LLC
Inventor： Ravi Kumar , Deepanshu Dutta , Vishwanath Basavaegowda Shanthakumar
Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to a word line and arranged in one of a plurality of blocks and configured to retain a threshold voltage corresponding to a data state. The memory cells are operable in one of a first read condition in which a word line voltage is discharged and a second read condition in which the word line voltage is coupled up to a residual voltage level. A control circuit determines a power on event and periodically apply a predetermined refresh read voltage to the word line for a predetermined period of time for each of the plurality of blocks at a specified interval based on at least one data retention factor to maintain the memory cells of the plurality of blocks in the second read condition in response to determining the power on event.
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公开(公告)号：US20220165341A1
公开(公告)日：2022-05-26
申请号：US17102954
申请日：2020-11-24
Applicant: SanDisk Technologies LLC
Inventor： Xue Bai Pitner , Dengtao Zhao , Deepanshu Dutta , Ravi Kumar
Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells. Each of the memory cells is connected to one of a plurality of word lines and are also arranged in strings and configured to retain a threshold voltage within a common range of threshold voltages. A control circuit coupled to the plurality of word lines and the strings is configured to determine an erase upper tail voltage of a distribution of the threshold voltage of the memory cells following an erase operation. The erase upper tail voltage corresponds to a cycling condition of the memory cells. The control circuit is also configured to calculate a program voltage to apply to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells during a program operation based on the erase upper tail voltage.
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Patent Agency Ranking
公开(公告)号：US11177002B1
公开(公告)日：2021-11-16
申请号：US16916285
申请日：2020-06-30
Applicant: SanDisk Technologies LLC
Inventor： Xue Pitner , Ravi Kumar , Deepanshu Dutta
Abstract: A storage device including control circuitry, communicatively coupled to a non-volatile memory, configured to receive a parity bit that has been stored using a data structure, and to receive a first subset of host data that includes block data relating to a set of memory cells. The control circuitry may be configured to perform a read operation to identify a second subset of host data that includes additional block data relating to the set of memory cells. The control circuitry may be configured to decode the second subset of host data using the parity bit. The control circuitry may be configured to perform a write operation to write the block data to at least one or more memory cells that are part of the set of memory cells.
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公开(公告)号：US11972809B2
公开(公告)日：2024-04-30
申请号：US17682280
申请日：2022-02-28
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Yu-Chung Lien , Ravi Kumar , Xue Pitner
CPC classification number: G11C16/3427 , G11C16/0483 , G11C16/14 , G11C16/24 , G11C16/26 , H10B41/27 , H10B43/27
Abstract: A non-volatile semiconductor memory device includes non-volatile storage elements and one or more control circuits in communication with the non-volatile storage elements. The one or more control circuits are configured to determine for a program iteration of a program operation on a word line whether a condition is met and in response to determining that the condition is met, identify one or more memory cells of the word line that are in an erased state that have a threshold voltage higher than an erase threshold voltage and perform the program iteration of the program operation. The program iteration includes applying a first bitline inhibit voltage to bitlines connected to the identified one or more memory cells and a second bitline inhibit voltage to bitlines connected to one or more memory cells that are in the erased state that do not have a threshold voltage higher than the erase threshold voltage.
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公开(公告)号：US20240103742A1
公开(公告)日：2024-03-28
申请号：US17955018
申请日：2022-09-28
Applicant: SanDisk Technologies LLC
Inventor： Towhidur Razzak , Ravi Kumar , Abu Naser Zainuddin , Jiahui Yuan
IPC: G06F3/06
CPC classification number: G06F3/0625 , G06F3/0629 , G06F3/0679
Abstract: In order to lower the peak and average current through the channel (thereby lowering peak and average power consumption) during program-verify, which exhibits a word line dependency, the inventors propose to program dummy memory cells connected to a dummy word line before programming data memory cells connected to a data word line. The additional resistance in the NAND string introduced by the preprogrammed dummy memory cells will cause the peak current, and power consumption, to be lower. To address the word line dependency, the dummy memory cells connected to the dummy word line can be programmed to different threshold voltages based on which data word line is to be programmed. Thus, prior to programming data non-volatile memory cells connected to a particular data word line, the dummy memory cells are programmed to a threshold voltage that is chosen based on the position of the particular data word line.
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公开(公告)号：US20230386586A1
公开(公告)日：2023-11-30
申请号：US17826434
申请日：2022-05-27
Applicant: SanDisk Technologies LLC
Inventor： Sujjatul Islam , Ravi Kumar
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/08
Abstract: The memory device that includes a plurality of memory cells that are arranged in a plurality of word lines. A controller is in electrical communication with the plurality of memory cells. During programming, the controller detects a temperature of the memory device. The controller then programs the memory cells of a selected word line of the plurality of word lines in a plurality of program loops until programming is completed or until the plurality of program loops is greater than a maximum number of program loops. The maximum number of program loops is dependent on the temperature that is detected.
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公开(公告)号：US20230307071A1
公开(公告)日：2023-09-28
申请号：US17701320
申请日：2022-03-22
Applicant: SanDisk Technologies LLC
Inventor： Xue Bai Pitner , Yu-Chung Lien , Ravi Kumar , Jiahui Yuan , Bo Lei , Zhenni Wan
CPC classification number: G11C16/3459 , G11C16/3404 , G11C16/102 , G11C16/26
Abstract: The memory device includes a plurality of memory cells, which include a first set of memory cells and a second set of memory cells. A controller is in communication with the memory cells. The controller is configured to, in a first programming pass and then a second programming pass, program the memory cells of the first and second sets to respective final threshold voltages associated with a plurality of programmed data states. The controller is further configured to, in the first programming pass, verify the first set of memory cells at a first set of checkpoint data states and verify the second set of memory cells at a second set of checkpoint data states that is different than the first set of checkpoint data states.
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