公开(公告)号：US20210157607A1

公开(公告)日：2021-05-27

申请号：US16695759

申请日：2019-11-26

Applicant: SanDisk Technologies LLC

Inventor： Vijay Chinchole ,  Nisha Padattil Kuliyampattil ,  Sonam Agarwal ,  Akash Agarwal ,  Pavithra Devaraj ,  Yan Li

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/22 ,  G06F9/54 ,  G06F11/30 ,  G06F12/02

Abstract: A non-volatile memory apparatus and corresponding method of operation are provided. The apparatus includes non-volatile memory cells in an integrated circuit device along with a microcontroller in communication with the non-volatile memory cells. The microcontroller is configured to receive a memory operation command and in response, determine a condition value of one of a plurality of conditions associated with the memory operation command and whether the one of the plurality of conditions is dynamic. In parallel, the microcontroller determines and outputs an output value using the condition value. The microcontroller then determines whether the one the plurality of conditions has changed. If the one of the plurality of conditions is dynamic and has changed, the microcontroller determines an updated condition value and in parallel, compares the condition value and the updated condition value and determines and outputs an updated output value using the updated condition value and the comparison.

公开(公告)号：US20200295029A1

公开(公告)日：2020-09-17

申请号：US16889030

申请日：2020-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20190179568A1

公开(公告)日：2019-06-13

申请号：US16015624

申请日：2018-06-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Chi-Lin Hsu ,  Tai-Yuan Tseng ,  Yan Li ,  Hiroyuki Mizukoshi

IPC: G06F3/06 ,  G06F9/32

Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.

公开(公告)号：US10043558B2

公开(公告)日：2018-08-07

申请号：US15628417

申请日：2017-06-20

Applicant: SanDisk Technologies LLC

Inventor： Grishma Shah ,  Yan Li ,  Jian Chen ,  Kenneth Louie ,  Nian Niles Yang

IPC: G11C7/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C7/1009 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1063 ,  G11C11/56 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C2211/563 ,  G11C2216/20

Abstract: Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading from selected word lines in the planes. In one approach, different types of read operations are performed in different planes, such as a multi-level cell read, e.g., a lower, middle or upper page read and a single-level cell (SLC) read. When the read operation in one plane uses fewer read voltages than another plane, the read data can be output early from the one plane while read operations continue on the other plane. The external controller can also command a cache release for one plane after outputting data from the caches of another plane. Read voltages can be set for each plane in a respective set of registers.

公开(公告)号：US20230187014A1

公开(公告)日：2023-06-15

申请号：US17550352

申请日：2021-12-14

Applicant: SanDisk Technologies LLC

Inventor： Iris Lu ,  Yan Li ,  Ohwon Kwon

IPC: G11C29/54 ,  G11C7/06

CPC classification number: G11C29/54 ,  G11C7/065

Abstract: Technology is disclosed herein for testing circuitry that controls memory operations in a memory structure having non-volatile memory cells. The testing of the circuitry can be performed without the memory structure. The memory structure may reside on one semiconductor die, with sense blocks and a control circuit on another semiconductor die. The control circuit is able to perform die level control of memory operations in the memory structure. The control circuit may control the sense blocks to simulate sensing of non-volatile memory cells in the memory structure even though the sense blocks are not connected to the memory structure. The control circuit verifies correct operation of the semiconductor die based on the simulated sensing. For example, the control circuit may verify correct operation of a state machine that controls sense operations at a die level. Thus, the operation of the semiconductor die may be tested without the memory structure.

公开(公告)号：US20210279169A1

公开(公告)日：2021-09-09

申请号：US16906233

申请日：2020-06-19

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Yan Li

IPC: G06F12/02 ,  G06F1/24 ,  G06F9/30 ,  G06F12/0877 ,  G06F13/16 ,  G06F9/445

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

公开(公告)号：US20210279168A1

公开(公告)日：2021-09-09

申请号：US16810243

申请日：2020-03-05

Applicant: SanDisk Technologies LLC

Inventor： Yuheng Zhang ,  Yan Li

IPC: G06F12/02 ,  G06F12/0877 ,  G06F13/16 ,  G06F9/30 ,  G06F9/445 ,  G06F1/24

Abstract: An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.

公开(公告)号：US20210182178A1

公开(公告)日：2021-06-17

申请号：US16712593

申请日：2019-12-12

Applicant: SanDisk Technologies LLC

Inventor： Masakazu EHAMA ,  Hiroyuki Mizukoshi ,  Yan Li

IPC: G06F11/36 ,  G11C16/30 ,  G06F9/22 ,  G06F9/26 ,  G06F9/24

Abstract: A 3D NAND memory device is provided in which control is performed by two microcontroller units (MCU). During manufacture of the memory device, bug fixes required for the controller may be addressed using a software solution by which an instruction requiring correction in one of the two MCUs is replaced with a corrected instruction stored in a RAM.

公开(公告)号：US10707228B2

公开(公告)日：2020-07-07

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/088 ,  H01L27/11578 ,  G11C5/02 ,  G11C5/06

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.

公开(公告)号：US20200066745A1

公开(公告)日：2020-02-27

申请号：US16284502

申请日：2019-02-25

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jixin Yu ,  Tae-Kyung Kim ,  Johann Alsmeier ,  Yan Li ,  Jian Chen

IPC: H01L27/11578 ,  G11C5/06 ,  G11C5/02

Abstract: Three-dimensional memory devices in the form of a memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack, in which each of the memory stack structures includes a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. Bit lines are electrically connected to an end portion of a respective one of the vertical semiconductor channels. Bump connection via structures contact a top surface of a respective one of the bit lines, in which each of the bump connection via structures has a greater lateral dimension along a lengthwise direction of the bit lines than along a widthwise direction of the bit lines. Metallic bump structures of another semiconductor die contact respective ones of the bump connection via structures to make respective electrical connections between the two dies.