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公开(公告)号：US11694755B2
公开(公告)日：2023-07-04
申请号：US17337329
申请日：2021-06-02
Applicant: SanDisk Technologies LLC
Inventor： Hiroyuki Mizukoshi , Heguang Li , Althaf Rahamathulla , Qihan Li
CPC classification number: G11C16/3481 , G11C16/102 , G11C16/26 , G11C16/3459 , G11C29/021
Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.
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公开(公告)号：US11301176B2
公开(公告)日：2022-04-12
申请号：US16909484
申请日：2020-06-23
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/30 , G06F9/38 , G11C11/00 , G11C5/06 , G11C11/4072 , G06F8/65 , G11C29/16 , G11C5/14 , G11C16/28 , G11C11/56 , G11C29/46 , G11C16/34 , G11C16/24 , G11C16/10 , G11C16/08
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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公开(公告)号：US20190179568A1
公开(公告)日：2019-06-13
申请号：US16015624
申请日：2018-06-22
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.
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公开(公告)号：US20200341691A1
公开(公告)日：2020-10-29
申请号：US16909467
申请日：2020-06-23
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/30 , G06F9/38 , G11C11/00 , G11C5/06 , G11C11/4072 , G06F8/65 , G11C29/16 , G11C5/14 , G11C16/28 , G11C11/56 , G11C29/46 , G11C16/34 , G11C16/24 , G11C16/10 , G11C16/08
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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公开(公告)号：US20190179573A1
公开(公告)日：2019-06-13
申请号：US15994116
申请日：2018-05-31
Applicant: SanDisk Technologies LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit includes a programmable and reprogrammable microcontroller. The microcontroller has a first processor that executes instructions to coordinate sequences of voltages applied to the memory structure by a first circuit in order to perform memory operations. The microcontroller has a second processor that executes second instructions to control a second circuit to test conditions of the non-volatile memory cells in response to the voltages applied to the memory structure. The microcontroller may have a third processor that controls the flow of the memory operation and directs the first and second processors to execute the instructions. The instructions of the various processors may be updated, which provides for flexible flow, core operation control, and condition testing.
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Patent Agency Ranking
公开(公告)号：US20190179532A1
公开(公告)日：2019-06-13
申请号：US16003515
申请日：2018-06-08
Applicant: SANDISK TECHNOLOGIES LLC?
Inventor： Tai-Yuan Tseng , Hiroyuki Mizukoshi , Chi-Lin Hsu , Yan Li
Abstract: An apparatus includes a first processor that generates first control signals to control a first circuit to perform memory operations on memory cells. A first number of first physical signal lines delivers the first control signals to a conversion circuit. A second number of second physical signal lines delivers converted control signals to the first circuit. The conversion circuit is coupled by the first number of first physical signal lines to the first processor and by the second number of second physical signal lines to the first circuit. The conversion circuit converts the first control signals to the converted control signals, and outputs the converted control signals to the first circuit. The first number of first physical signal lines is less than the second number of second physical signal lines to reduce the first number of first physical signal lines coupled between the first processor and the first circuit.
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7.发明授权公开(公告)号：US12057175B2
公开(公告)日：2024-08-06
申请号：US17715647
申请日：2022-04-07
Applicant: SanDisk Technologies LLC
Inventor： Chin-Yi Chen , Muhammad Masuduzzaman , Kou Tei , Deepanshu Dutta , Hiroyuki Mizukoshi , Jiahui Yuan , Xiang Yang
CPC classification number: G11C16/26 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/3459 , G11C11/5621 , G11C11/5671
Abstract: A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines. The memory cells are disposed in memory holes and grouped into a plurality of tiers. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states to store one bit as single-level cells and a plurality of bits as multi-level cells. The apparatus also includes a control means coupled to the word lines and the memory holes and configured to select a predetermined strobe quantity of the plurality of tiers of the memory cells separately for the memory cells operating as the single-level cells and the memory cells operating as the multi-level cells. The control means is also configured to trigger sensing of the predetermined strobe quantity of the plurality of tiers of the memory cells during a verify operation.
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公开(公告)号：US10725699B2
公开(公告)日：2020-07-28
申请号：US16015624
申请日：2018-06-22
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Chi-Lin Hsu , Tai-Yuan Tseng , Yan Li , Hiroyuki Mizukoshi
IPC: G06F3/06 , G06F9/32 , G11C16/10 , G11C11/56 , G11C16/26 , G11C16/32 , G11C16/34 , G06F13/00 , G11C16/08 , G11C16/24 , G11C16/04
Abstract: An apparatus is provided that includes a processor and an instruction memory including a first memory, a second memory, a third memory and an instruction selector circuit. The first memory is configured to receive a first instruction address from the processor, the second memory is configured to receive the first instruction address from the processor and generate a control signal based on the received first instruction address, and the third memory is configured to receive the first instruction address from the processor. The instruction selector circuit is configured to selectively send an instruction from one of the first memory and the third memory based on the control signal to the processor, and to selectively enable and disable the third memory to reduce power consumption of the instruction memory.
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公开(公告)号：US20180357123A1
公开(公告)日：2018-12-13
申请号：US15934565
申请日：2018-03-23
Applicant: SanDisk Technologies LLC
Inventor： Yibo Yin , Henry Zhang , Po-Shen Lai , Vijay Chinchole , Spyridon Georgakis , Yan Li , Hiroyuki Mizukoshi , Toru Miwa , Jayesh Pakhale , Tz-Yi Liu
IPC: G06F11/10
CPC classification number: G06F11/1016 , G06F11/1064
Abstract: Apparatuses, systems, methods, and computer program products are disclosed for a multicore on-die memory controller. An integrated circuit device includes an array of non-volatile memory cells and a microcontroller unit. A microcontroller unit includes a plurality of processing units. Different processing units perform different categories of tasks in parallel for an array of non-volatile memory cells.
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公开(公告)号：US20220392555A1
公开(公告)日：2022-12-08
申请号：US17337329
申请日：2021-06-02
Applicant: SanDisk Technologies LLC
Inventor： Hiroyuki Mizukoshi , Heguang Li , Althaf Rahamathulla , Qihan Li
Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.
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