公开(公告)号：US06822328B2

公开(公告)日：2004-11-23

申请号：US10229865

申请日：2002-08-27

申请人： Gurtej S. Sandhu ,  Ravi Iyer

发明人： Gurtej S. Sandhu ,  Ravi Iyer

IPC分类号： H01L2348

CPC分类号： H01L21/76843 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685

摘要： The invention includes integrated circuitry having an electrically insulative layer over a substrate and an opening within the electrically insulative layer. The opening has a periphery defined at least in part by a bottom surface and a sidewall surface. A first titanium layer is disposed within the opening in contact with the bottom surface and is thicker along the bottom surface than along the sidewall. A layer of TiN is provided over the first titanium layer along the bottom surface and along the sidewall surface of the opening, and a second layer of titanium is disposed over the electrically insulative layer but substantially not within the opening. The second titanium layer has a thickness of less then 50 Å along the sidewall surface and over the bottom surface. An aluminum-comprising layer is within the opening and over the second layer.

摘要翻译： 本发明包括在基板上具有电绝缘层的集成电路和电绝缘层内的开口。 开口具有至少部分地由底表面和侧壁表面限定的外围。 第一钛层设置在与底表面接触的开口内，并且沿着底表面比沿侧壁更厚。 沿着底表面并沿着开口的侧壁表面在第一钛层上提供TiN层，并且第二层钛层设置在电绝缘层上，但基本上不在开口内。 第二钛层的侧壁表面和底面的厚度小于50埃。 包含铝的层在开口内和第二层之上。

公开(公告)号：US06544876B1

公开(公告)日：2003-04-08

申请号：US09635082

申请日：2000-08-08

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L2100

CPC分类号： H01L29/4941 ,  H01L21/28061 ,  H01L21/76895

摘要： A method for use in the fabrication of a gate electrode includes providing a gate oxide layer and forming a titanium boride layer on the oxide layer. An insulator cap layer is formed on the titanium boride layer and thereafter, the gate electrode is formed from the titanium boride layer. A barrier layer may be formed on the oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the barrier layer and the titanium boride layer. Further, a polysilicon layer may be formed on the gate oxide layer prior to forming the titanium boride layer with the gate electrode being formed from the titanium boride layer and the polysilicon layer. Yet further, a polysilicon layer may be formed on the gate oxide layer and a barrier layer formed on the polysilicon layer prior to forming the titanium boride layer. The gate electrode is then formed from the polysilicon layer, the barrier layer, and the titanium boride layer. Similar methods can further be used in the formation of interconnects to connect contact regions. Gate electrode structures and interconnect structures resulting from the methods are also described. Further, in such methods and structures, the titanium boride layer may be a titanium diboride layer or a titanium boride layer having silicon incorporated therein.

摘要翻译： 用于制造栅电极的方法包括提供栅极氧化层并在氧化物层上形成硼化钛层。 在硼化钛层上形成绝缘体盖层，之后，由硼化钛层形成栅电极。 在形成硼化钛层之前，可以在氧化物层上形成阻挡层，其中栅电极由阻挡层和硼化钛层形成。 此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层，其中栅电极由硼化钛层和多晶硅层形成。 此外，在形成硼化钛层之前，可以在栅极氧化物层上形成多晶硅层和在多晶硅层上形成的势垒层。 然后，由多晶硅层，阻挡层和硼化钛层形成栅电极。 类似的方法可以进一步用于形成互连以连接接触区域。 还描述了由该方法产生的栅电极结构和互连结构。 此外，在这些方法和结构中，硼化钛层可以是二硼化钛层或其中掺入硅的硼化钛层。

公开(公告)号：US06365530B1

公开(公告)日：2002-04-02

申请号：US09645958

申请日：2000-08-24

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/316 ,  H01L21/31612

摘要： The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

公开(公告)号：US06337286B1

公开(公告)日：2002-01-08

申请号：US09258741

申请日：1999-02-26

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L2100

CPC分类号： H01L21/67069 ,  H01L21/32136

摘要： A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.

摘要翻译： 一种用于等离子体蚀刻金属膜的方法，包括以下步骤：形成惰性气体等离子体，然后将稀有气体等离子体输送到混合室。 在混合室中的惰性气体等离子体中加入有机卤化物。 选择有机卤化物具有允许形成活化复合物的蒸汽压力以蚀刻金属膜并形成有机金属化合物作为蚀刻副产物。 如此形成的活化的复合体在下游被传送到蚀刻室。 在蚀刻室中，所选择的基底暴露于活化的复合物，导致基底被蚀刻，并且有机金属化合物由于活化复合物的反应和基底的蚀刻而被形成为副产物。 然后可以从蚀刻室中除去有机金属副产物。

公开(公告)号：US06333536B1

公开(公告)日：2001-12-25

申请号：US09702584

申请日：2000-10-31

申请人： Ravi Iyer ,  Luan Tran ,  Charles L. Turner

发明人： Ravi Iyer ,  Luan Tran ,  Charles L. Turner

IPC分类号： H01L27108

CPC分类号： H01L27/1085 ,  H01L21/76895 ,  H01L28/84

摘要： A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

公开(公告)号：US6144098A

公开(公告)日：2000-11-07

申请号：US744298

申请日：1996-11-06

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L21/316 ,  H01L29/40

CPC分类号： H01L21/02164 ,  H01L21/02304 ,  H01L21/02315 ,  H01L21/316 ,  H01L21/31612

摘要： The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

公开(公告)号：US6087254A

公开(公告)日：2000-07-11

申请号：US682935

申请日：1996-07-16

申请人： Pai-Hung Pan ,  Louie Liu ,  Ravi Iyer

发明人： Pai-Hung Pan ,  Louie Liu ,  Ravi Iyer

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28052

摘要： A method for forming a gate stack which minimizes or eliminates damage to the gate dielectric layer and/or silicon substrate during the gate stack formation by the reduction of the temperature during formation. The temperature reduction prevents the formation of silicon clusters within the metallic silicide film in the gate stack which has been found to cause damage during the gate etch step. The present invention also includes methods for dispersing silicon clusters prior to the gate etch step.

公开(公告)号：US6033992A

公开(公告)日：2000-03-07

申请号：US918593

申请日：1997-08-19

申请人： Ravi Iyer

发明人： Ravi Iyer

IPC分类号： H01L21/00 ,  H01L21/3213

CPC分类号： H01L21/67069 ,  H01L21/32136

摘要： A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.

公开(公告)号：US5985770A

公开(公告)日：1999-11-16

申请号：US915987

申请日：1997-08-21

申请人： Gurtej S. Sandhu ,  Ravi Iyer

发明人： Gurtej S. Sandhu ,  Ravi Iyer

IPC分类号： C23C16/30 ,  H01L21/316 ,  H01L21/368

CPC分类号： H01L21/02271 ,  C23C16/30 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/0214 ,  H01L21/31612

摘要： The invention comprises methods of depositing silicon oxide material onto a substrate. In but one aspect of the invention, a method of depositing a silicon oxide containing layer on a substrate includes initially forming a layer comprising liquid silicon oxide precursor onto a substrate. After forming the layer, the layer is doped and transformed into a solid doped silicon oxide containing layer on the substrate. In a preferred implementation, the doping is by gas phase doping and the liquid precursor comprises Si(OH).sub.4. In the preferred implementation, the transformation occurs by raising the temperature of the deposited liquid precursor to a first elevated temperature and polymerizing the deposited liquid precursor on the substrate. The temperature is continued to be raised to a second elevated temperature higher than the first elevated temperature and a solid doped silicon oxide containing layer is formed on the substrate.

公开(公告)号：US5963835A

公开(公告)日：1999-10-05

申请号：US977786

申请日：1997-11-25

申请人： Gurtej S. Sandhu ,  Ravi Iyer

发明人： Gurtej S. Sandhu ,  Ravi Iyer

IPC分类号： H01L23/485 ,  H01L23/532 ,  H01L21/70

CPC分类号： H01L23/53223 ,  H01L23/485 ,  H01L2924/0002

摘要： A method for depositing an aluminum film limits the growth of voids and notches in the aluminum film and forms and aluminum film with a reduced amount of voids and notches. The first step of the method is to form an underlying layer upon which is deposited an aluminum film having a first thickness. The surface of the aluminum film is then exposed to a passivation species which coats the aluminum grains and precipitates at the grain boundaries so as to prevent grain movement. The exposure of the aluminum film to the passivation species reduces void formation and coalescence of the voids. An aluminum layer having a second thickness is then deposited over the initially deposited aluminum layer. In a second embodiment of the invention, the passivation species is deposited with MOCVD and to form an electromigration-resistant alloy. A third embodiment involves multiple depositions of aluminum, with exposure to a passivation species conducted after each deposition. Each deposition is also conducted at a successively lower temperature than the prior deposition.

摘要翻译： 铝膜的沉积方法限制了铝膜中的空隙和凹口的生长，并形成了具有减少量的空隙和凹口的铝膜。 该方法的第一步是形成下层，沉积具有第一厚度的铝膜。 然后将铝膜的表面暴露于钝化物质，其涂覆铝颗粒并在晶界处沉淀，以防止颗粒移动。 铝膜暴露于钝化物质可以减少空隙的形成和孔隙的聚结。 然后在初始沉积的铝层上沉积具有第二厚度的铝层。 在本发明的第二个实施方案中，钝化物质用MOCVD沉积并形成耐电迁移合金。 第三个实施例涉及铝的多次沉积，暴露于在每次沉积之后进行的钝化物质。 每次沉积也在比先前的沉积相继低的温度下进行。