公开(公告)号：US06329257B1

公开(公告)日：2001-12-11

申请号：US08994140

申请日：1997-12-19

Applicant: Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

Inventor： Scott D. Luning ,  Daniel Sobek ,  Timothy J. Thurgate

IPC: H01L21336

CPC classification number: H01L29/0847 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/36 ,  H01L29/7883

Abstract: A system and method for controlling a characteristic of at least one memory cell on a semiconductor is disclosed. The at least one memory cell includes a gate stack, a source, and a drain. The semiconductor includes a surface. In one aspect, the method and system include providing the gate stack on the semiconductor and providing the source including a source dopant having a local peak in concentration. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor. In another aspect the method and system includes a memory cell on a semiconductor. The semiconductor includes a surface. The memory cell includes a gate stack on the semiconductor, a source, and a drain. The gate stack has a first edge and a second edge. The source is located in proximity to the first edge of the gate stack. The drain is located in proximity to the second edge of the gate stack. A first portion of the source is disposed under the gate stack. The source includes a source dopant having a local peak in concentration of the source dopant. The local peak in concentration of the source dopant is located under the gate stack and in proximity to a portion of the surface of the semiconductor.

Abstract translation: 公开了一种用于控制半导体上的至少一个存储单元的特性的系统和方法。 所述至少一个存储单元包括栅极堆叠，源极和漏极。 半导体包括表面。 在一个方面，所述方法和系统包括在半导体上提供栅极堆叠并且提供源，其包括具有局部峰浓度的源掺杂剂。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。 在另一方面，该方法和系统包括半导体上的存储单元。 半导体包括表面。 存储单元包括半导体上的栅极堆叠，源极和漏极。 栅极堆叠具有第一边缘和第二边缘。 源极位于栅堆叠的第一边缘附近。 漏极位于栅堆叠的第二边缘附近。 源极的第一部分设置在栅极堆叠下方。 该源包括源掺杂剂，其具有源掺杂剂浓度的局部峰。 源掺杂剂的局部峰浓度位于栅极堆叠之下并且靠近半导体表面的一部分。

公开(公告)号：US6153487A

公开(公告)日：2000-11-28

申请号：US40107

申请日：1998-03-17

Applicant: Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

Inventor： Scott D. Luning ,  Timothy J. Thurgate ,  Daniel Sobek ,  Nicholas H. Tripsas

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/22 ,  H01L21/38 ,  H01L29/76

CPC classification number: H01L29/66825 ,  H01L21/2652

Abstract: The present invention provides a method and system for the formation of semiconductor devices which reduces band-to-band tunneling current and short-channel effects. The method and system includes implanting first low-dose arsenic into an area in the substrate, thermally diffusing the first low-dose arsenic through a portion of the substrate, implanting a second higher-dose arsenic into the area in the substrate, and diffusing the second higher-dose arsenic into the area in the substrate. Under the present invention, the combination of the first and second arsenic implants has a graded lateral profile which reduces band-to-band tunneling current and short-channel effects. The method also improves the reliability and performance of the semiconductor devices.

Abstract translation: 本发明提供一种用于形成半导体器件的方法和系统，其减少带间隧穿电流和短沟道效应。 该方法和系统包括将第一低剂量砷注入到衬底中的区域中，通过衬底的一部分热扩散第一低剂量砷，将第二较高剂量的砷注入到衬底的区域中， 第二高剂量砷进入底物区域。 在本发明中，第一和第二砷植入物的组合具有梯度横向轮廓，其降低带对隧道电流和短通道效应。 该方法还提高了半导体器件的可靠性和性能。

公开(公告)号：US6005808A

公开(公告)日：1999-12-21

申请号：US993570

申请日：1997-12-18

Applicant: Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

Inventor： Daniel Sobek ,  Timothy James Thurgate ,  Scott D. Luning ,  Vei-Han Chan ,  Sameer S. Haddad

Abstract: A method and apparatus for reducing band-to-band currents during the erasure of a flash EEPROM memory cell is provided. The apparatus has a back biasing connection on the substrate at which a biasing voltage is applied during erasure of the flash EEPROM memory cell. The method of applying the biasing voltage to the back biasing connection during erasure of the flash EEPROM memory cell reduces band-to-band current between the source region and the substrate during erasure of the flash memory cell. This reduction provides for gate size reduction in flash memory cells without inducing detrimental short channel effects.

公开(公告)号：US09373548B2

公开(公告)日：2016-06-21

申请号：US12199659

申请日：2008-08-27

Applicant: Gen Pei ,  Scott D. Luning ,  Johannes van Meer

Inventor： Gen Pei ,  Scott D. Luning ,  Johannes van Meer

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/7843

Abstract: A CMOS circuit is provided that includes a PMOS transistor, an NMOS transistor adjacent the PMOS transistor in a channel width direction, a compressive stress liner overlying the PMOS transistor, and a tensile stress liner overlying the NMOS transistor. A portion of the compressive stress liner and a portion of the tensile stress liner are in a stacked configuration, and an overlap region of the compressive stress liner and the tensile stress liner is sufficient to result in an enhanced transverse stress in the compressive stress liner or the tensile stress liner.

Abstract translation: 提供了一种CMOS电路，其包括PMOS晶体管，在沟道宽度方向上与PMOS晶体管相邻的NMOS晶体管，覆盖PMOS晶体管的压应力衬垫以及覆盖NMOS晶体管的拉伸应力衬垫。 压缩应力衬垫的一部分和拉伸应力衬垫的一部分处于堆叠构型，并且压应力衬垫和拉伸应力衬垫的重叠区域足以导致压缩应力衬垫中的增强的横向应力或 拉伸应力衬垫。

公开(公告)号：US07572705B1

公开(公告)日：2009-08-11

申请号：US11231647

申请日：2005-09-21

Applicant: Paul R. Besser ,  Scott D. Luning

Inventor： Paul R. Besser ,  Scott D. Luning

IPC: H01L21/336

CPC classification number: H01L29/66628 ,  H01L29/66772

Abstract: A semiconductor device is disclosed having a conductive gate structure overlying a semiconductor layer having a major surface. An isolation material is recessed within a trench region below the major surface of the semiconductor layer. An epitaxial layer is formed overlying a portion of the major surface and on an active region forming a sidewall of the trench.

Abstract translation: 公开了一种半导体器件，其具有覆盖具有主表面的半导体层的导电栅极结构。 隔离材料凹陷在半导体层的主表面下方的沟槽区域内。 形成外延层，覆盖主表面的一部分和形成沟槽侧壁的有源区。

公开(公告)号：US07442601B2

公开(公告)日：2008-10-28

申请号：US11532753

申请日：2006-09-18

Applicant: Gen Pei ,  Scott D. Luning ,  Johannes van Meer

Inventor： Gen Pei ,  Scott D. Luning ,  Johannes van Meer

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/092 ,  H01L29/7843

Abstract: A stress enhanced CMOS circuit and methods for its fabrication are provided. One fabrication method comprises the steps of forming an NMOS transistor and a PMOS transistor adjacent the NMOS transistor in a channel width direction, the PMOS transistor and the NMOS transistor separated by an isolation region. A compressive stress liner is deposited overlying the transistors and the isolation region and is etched to remove the compressive stress liner from the NMOS transistor and from a portion of the isolation region. A tensile stress liner is deposited overlying the transistors, the isolation region, and the compressive stress liner and is etched to remove a portion of the tensile stress liner overlying a portion of the compressive stress liner and to leave the tensile stress liner overlying the NMOS transistor, the isolation region, and a portion of the compressive stress liner.

Abstract translation: 提供了一种应力增强CMOS电路及其制造方法。 一种制造方法包括以下步骤：在沟道宽度方向上形成与NMOS晶体管相邻的NMOS晶体管和PMOS晶体管，PMOS晶体管和NMOS晶体管由隔离区隔开。 压缩应力衬垫沉积在晶体管和隔离区上，并被蚀刻以从NMOS晶体管和隔离区的一部分去除压应力衬垫。 拉伸应力衬垫沉积在晶体管，隔离区域和压缩应力衬垫上，并被蚀刻以去除覆盖压缩应力衬垫的一部分的拉伸应力衬垫的一部分，并且留下覆盖NMOS晶体管的拉伸应力衬垫 ，隔离区域和压缩应力衬垫的一部分。

公开(公告)号：US07402485B1

公开(公告)日：2008-07-22

申请号：US11229864

申请日：2005-09-19

Applicant: William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Scott D. Luning

Inventor： William G. En ,  Thorsten Kammler ,  Eric N. Paton ,  Scott D. Luning

IPC: H01L21/8238

CPC classification number: H01L29/6656 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

Abstract: A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

Abstract translation: 侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。 在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。 在清洁处理之后形成外延层。

公开(公告)号：US06777281B1

公开(公告)日：2004-08-17

申请号：US10214361

申请日：2002-08-08

Applicant: Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

Inventor： Daniel Kadosh ,  Scott D. Luning ,  Akif Sultan ,  David Wu

IPC: H01L218238

CPC classification number: H01L29/6659 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/823814 ,  H01L29/6656

Abstract: A method of manufacturing a semiconductor device, comprising steps of: (a) providing a semi conductor substrate including at least one dopant species-containing region extending to a surface of the substrate; (b) forming a thin liner oxide layer on the surface of the substrate; and (c) incorporating in the thin line oxide layer at least one species which substantially prevents, or at least reduces, segregation therein of the dopant species arising from movement thereinto from the at least one dopant species-containing region.

Abstract translation: 一种制造半导体器件的方法，包括以下步骤：（a）提供半导体衬底，其包括至少一个延伸到衬底表面的含掺杂物种的区域;（b）在衬底的表面上形成薄的衬里氧化物层 基材; 和（c）在细线氧化物层中并入至少一种物质，其至少一种物质，其基本上防止或至少减少其中从至少一种含掺杂物种的区域移动而引起的掺杂物质的偏析。

公开(公告)号：US06727558B1

公开(公告)日：2004-04-27

申请号：US09784790

申请日：2001-02-15

Applicant: Michael P. Duane ,  David D. Wu ,  Massud Aminpur ,  Scott D. Luning

Inventor： Michael P. Duane ,  David D. Wu ,  Massud Aminpur ,  Scott D. Luning

IPC: H01L21425

CPC classification number: H01L29/0847 ,  H01L21/28123 ,  H01L21/823412 ,  H01L21/823481 ,  H01L29/1079 ,  H01L29/51 ,  H01L29/518 ,  H01L29/665 ,  H01L29/6659

Abstract: A method is provided, the method including forming a gate dielectric above a substrate layer, and forming a gate conductor above the gate dielectric. The method also includes forming at least one dielectric isolation structure in the substrate adjacent the gate dielectric.

Abstract translation: 提供了一种方法，该方法包括在衬底层上形成栅极电介质，以及在栅极电介质上方形成栅极导体。 该方法还包括在邻近栅极电介质的衬底中形成至少一个电介质隔离结构。

公开(公告)号：US06506642B1

公开(公告)日：2003-01-14

申请号：US10020931

申请日：2001-12-19

Applicant: Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

Inventor： Scott D. Luning ,  Jon D. Cheek ,  Daniel Kadosh ,  James F. Buller ,  David E. Brown

IPC: H01L218238

CPC classification number: H01L29/6653 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656

Abstract: Submicron-dimensioned MOS and/or CMOS transistors are fabricated utilizing a simplified removable sidewall spacer technique, enabling effective tailoring of individual transistors to optimize their respective functionality. Embodiments include forming a first sidewall spacer having a first thickness on the side surfaces of a plurality of gate electrodes of transistors, selectively removing the first sidewall spacers from the gate electrodes of certain transistors, and then depositing second sidewall spacers on remaining first sidewall spacers and on the side surfaces of the gate electrodes from which the first sidewall spacers have been removed. Embodiments enable separately tailoring n- and p-MOS transistors as well as individual n- or p-MOS transistors having different functionality, e.g., different drive current and voltage leakage requirements.

Abstract translation: 亚微米尺寸的MOS和/或CMOS晶体管使用简化的可移除侧壁间隔物技术制造，使得能够有效地定制各个晶体管以优化它们各自的功能。 实施例包括在晶体管的多个栅极电极的侧表面上形成具有第一厚度的第一侧壁间隔物，从某些晶体管的栅电极选择性地去除第一侧壁间隔物，然后在剩余的第一侧壁间隔物上沉积第二侧壁间隔物， 在栅电极的已经被去除了第一侧壁间隔物的侧表面上。 实施例能够单独定制n型和p型MOS晶体管以及具有不同功能的单独n型或p型MOS晶体管，例如不同的驱动电流和电压泄漏要求。