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公开(公告)号：US20200005819A1
公开(公告)日：2020-01-02
申请号：US16570785
申请日：2019-09-13
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , H03L7/091 , H03M1/00 , G11B20/10 , H03L7/081 , H03L7/07 , H03K5/131 , H03K5/135 , H03M13/41
Abstract: An apparatus may include a circuit configured to receive first and second samples of an underlying data from respective first and second sample periods and which correspond to respective first and second sensors, a phase control value may have first and second values during respective first and second sample periods. The phase control value may be a control value for a sample clock signal. The circuit may also determine a difference in the phase control value between the first value and the second value. The circuit may then digitally interpolate the first and second samples to produce a phase shifted first and second samples where the digital interpolation of at least one of the first and second samples mat be at least in part based on the difference in the phase control value to compensate for a phase misalignment between the first sample and the second sample.
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公开(公告)号：US20240144959A1
公开(公告)日：2024-05-02
申请号：US18405516
申请日：2024-01-05
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/09 , G06F13/385 , H03M1/12 , G11B2005/0013
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry (MRA) compensation using a digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end circuit, and performing analog offset compensation to constrain the extrema of the analog signal to adjust a dynamic range based on an input range of an analog-to-digital converter (ADC), rather than to modify the analog signal to have a zero mean. The method may further comprise converting the analog signal to a digital sample sequence via the ADC; performing, via a digital MRA compensation circuit, digital MRA compensation on the digital sample sequence; receiving, via a digital backend (DBE) subsystem, the digital sample sequence prior to digital MRA compensation; and generating, via a DBE, a bit sequence corresponding to the analog signal based on an output of the DBE subsystem and an output of the digital MRA compensation circuit.
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公开(公告)号：US11361788B2
公开(公告)日：2022-06-14
申请号：US16672718
申请日：2019-11-04
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
IPC: G11B5/596 , G11B20/10 , G06F13/10 , G06F13/42 , G06F1/08 , G06F1/12 , H04L25/03 , H03L7/093 , H03L7/095 , H03L7/07 , H03L7/081 , H03L7/091 , H04L7/00 , H04L7/033 , H03K5/131 , H03M1/00 , H03M13/41 , H03K5/135 , H03G3/20 , H03M1/12 , H03M13/29 , H04B1/7105 , H03K5/00
Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.
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公开(公告)号：US11341998B1
公开(公告)日：2022-05-24
申请号：US17016484
申请日：2020-09-10
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Marcus Marrow , Jason Bellorado
Abstract: Systems and methods are disclosed for hardware-based read sample averaging in a data storage device. In one example, a read channel circuit including a buffer memory is configured to receive a read instruction to read a selected sector, obtain detected sample values for the selected sector, and determine whether the read instruction corresponds to a re-read operation for the selected sector based on determining whether there are stored samples for the selected sector already stored to a locked buffer entry of the buffer memory. When there are stored sample values stored to the locked buffer entry, the example read channel circuit determines the re-read operation is occurring, and performs read sample averaging based on the detected sample values and the stored sample values to produce averaged sample values. Other examples and configurations are also described.
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公开(公告)号：US20200065262A1
公开(公告)日：2020-02-27
申请号：US16672718
申请日：2019-11-04
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: Systems and methods are disclosed for full utilization of a data path's dynamic range. In certain embodiments, an apparatus may comprise a circuit including a first filter to digitally filter and output a first signal, a second filter to digitally filter and output a second signal, a summing node, and a first adaptation circuit. The summing node combine the first signal and the second signal to generate a combined signal at a summing node output. The first adaptation circuit may be configured to receive the combined signal, and filter the first signal and the second signal to set a dynamic amplitude range of the combined signal at the summing node output by modifying a first coefficient of the first filter and a second coefficient of the second filter based on the combined signal.
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Patent Agency Ranking
公开(公告)号：US10559321B1
公开(公告)日：2020-02-11
申请号：US16274669
申请日：2019-02-13
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Jason Bellorado , Marcus Marrow , Vincent B Ashe
Abstract: In one implementation, the disclosure provides a system including a first circuit to compute a timing error based on a received error signal and an estimated interference signal and a timing loop filter to output a frequency offset and a phase shift based on the timing error received as input. The system also includes a phase accumulator to accumulate at least a phase shift to generate a sample index and phase and an interpolation filter to generate samples of a side track signal using the sample index and phase.
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公开(公告)号：US20180366155A1
公开(公告)日：2018-12-20
申请号：US15791190
申请日：2017-10-23
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
Abstract: An apparatus may include a circuit configured to receive a first phase control value of a phase control value signal, generate a first phase interpolator control signal value of a phase interpolator control signal and generate a first digital interpolator control signal value of a digital interpolator control signal. The apparatus may further be configured to phase interpolate a clock signal based on the first phase interpolator control signal value to produce a phase shifted clock signal and digitally interpolate a digital sample based on the first digital interpolator signal value to produce a phase shifted digital sample having an effective phase based on the first phase control value, the digital sample generated using the phase shifted clock signal as a sample clock.
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公开(公告)号：US10157637B1
公开(公告)日：2018-12-18
申请号：US15722641
申请日：2017-10-02
Applicant: Seagate Technology LLC
Inventor： Marcus Marrow , Jason Bellorado , Zheng Wu
Abstract: Systems and methods are disclosed for sampling signals in multi-reader magnetic recording. In certain embodiments, an apparatus may comprise a plurality of read heads configured to simultaneously read from a single track of a storage medium, a plurality of analog to digital converters (ADCs) configured to receive signal patterns from corresponding read heads, and a circuit configured to control the plurality of ADCs to sample the signal patterns according to a single clock signal generator. The output of the ADCs may be individually delayed based on a down-track offset of the read heads in order to align the samples, so that samples corresponding to the same portion of the recorded signal can be combined for bit pattern detection.
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公开(公告)号：US10014026B1
公开(公告)日：2018-07-03
申请号：US15713991
申请日：2017-09-25
Applicant: Seagate Technology LLC
Inventor： Zheng Wu , Marcus Marrow , Jason Bellorado
IPC: G11B20/10
CPC classification number: G11B5/59666 , G11B5/59633 , G11B20/10037 , G11B20/10055 , G11B20/10222 , G11B20/1024 , H03K5/131 , H03K5/135 , H03K2005/00019 , H03L7/07 , H03L7/0814 , H03L7/091 , H03M1/001 , H03M13/2951 , H03M13/4146 , H04B1/71055 , H04L7/0025 , H04L7/0029 , H04L7/0331
Abstract: Systems and methods are disclosed for head delay calibration and tracking multi-sensor magnetic recording (MSMR) systems. In certain embodiments, an apparatus may comprise a first reader and a second reader configured to simultaneously read from a single track of a data storage medium, the first reader offset from the second reader such that the first reader and the second reader detect a same signal pattern offset in time. The apparatus may further comprise a circuit configured to determine a relative offset between the first reader and the second reader, including setting a fixed delay for a first signal from the first reader, setting a second delay for a second signal from the second reader, and adjusting the second delay to align the second signal to the first signal using a timing loop, with the first signal used as a reference signal.
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公开(公告)号：US11900970B2
公开(公告)日：2024-02-13
申请号：US17162218
申请日：2021-01-29
Applicant: Seagate Technology LLC
Inventor： Jason Bellorado , Marcus Marrow , Zheng Wu
CPC classification number: G11B5/09 , G06F13/385 , H03M1/12 , G11B2005/0013
Abstract: Systems and methods are disclosed for magnetoresistive asymmetry compensation using a hybrid analog and digital compensation scheme. In certain embodiments, a method may comprise receiving an analog signal at a continuous-time front end (CTFE) circuit, and performing, via the CTFE circuit, first magnetoresistive asymmetry (MRA) compensation on the analog signal to adjust the dynamic range of the analog signal based on an input range of an analog-to-digital converter (ADC). The method may further comprise converting the analog signal to a digital sample sequence via the ADC, and performing, via a digital MRA compensation circuit, second MRA compensation to correct residual MRA in the digital sample sequence. Offset compensation may also be performed in both the analog and digital domains.
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