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公开(公告)号：US08392696B2
公开(公告)日：2013-03-05
申请号：US12767201
申请日：2010-04-26
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3237 , G06F1/324 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.
摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 辐条模块包括多个具有硬件地址的接口电路。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件包括对应于多个接口电路的多个驱动器模块。 处理模块基于多个接口电路中的每一个的硬件地址执行引导固件以配置多个驱动器模块。
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22.发明授权公开(公告)号：US08335229B1
公开(公告)日：2012-12-18
申请号：US12700100
申请日：2010-02-04
IPC分类号： H04L12/40
CPC分类号： G06F13/4226 , G06F13/36
摘要： In some embodiments, a method for supporting multiple devices on a high speed physical link may be described. An embedded device may assert a link request pin to request to transmit data on a multi-point communications link that may serve a plurality of embedded devices. A controlling device may receive the link request signal. When the controlling device finishes sending data on the link, it may address the plurality of embedded devices in a round robin format and may determine which device asserted the link request pin. The embedded device that asserted the link request pin may send an acknowledgement signal to the controlling device when it is addressed.
摘要翻译： 在一些实施例中，可以描述用于支持高速物理链路上的多个设备的方法。 嵌入式设备可以断言链路请求引脚以请求在可以服务于多个嵌入式设备的多点通信链路上传输数据。 控制装置可以接收链路请求信号。 当控制装置在链路上完成发送数据时，它可以以循环格式对多个嵌入式设备进行寻址，并且可以确定哪个设备断言了链路请求引脚。 断言链接请求引脚的嵌入式设备在寻址时可以向控制设备发送确认信号。
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公开(公告)号：US08127053B1
公开(公告)日：2012-02-28
申请号：US12917390
申请日：2010-11-01
申请人： Ofer Bar-Shalom , Mark N. Fullerton , Alon Tsafrir
发明人： Ofer Bar-Shalom , Mark N. Fullerton , Alon Tsafrir
CPC分类号： G06F13/28
摘要： A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.
摘要翻译： 主机设备包括外围控制模块，其包括从第一存储器接收数据的第一存储器寄存器和与第一存储器通信的直接存储器访问（DMA）模块。 主机设备还包括从第一存储器接收数据的主机控制模块。 主机设备还包括与第一存储器寄存器，主机控制模块和包括第一存储器阵列的第二存储器通信的DMA控制模块。 DMA控制模块将第一存储器阵列的内容与存储器寄存器的内容进行比较，并且基于比较控制从第一存储器到外围控制模块的数据传输。
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公开(公告)号：US07904943B2
公开(公告)日：2011-03-08
申请号：US11027913
申请日：2004-12-28
IPC分类号： G06F7/04
摘要： A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.
摘要翻译： 存储控制器包括命令指针寄存器。 命令指针寄存器指向存储器中的一系列命令，并且还包括用于指示命令链中的第一命令的安全状态的安全状态字段。 命令链中的每个命令还可以包括指示链中以下命令的安全状态的安全状态字段。
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公开(公告)号：US07827323B2
公开(公告)日：2010-11-02
申请号：US11953552
申请日：2007-12-10
申请人： Ofer Bar-Shalom , Mark N. Fullerton , Alon Tsafrir
发明人： Ofer Bar-Shalom , Mark N. Fullerton , Alon Tsafrir
CPC分类号： G06F13/28
摘要： A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.
摘要翻译： 主机设备包括外围控制模块，其包括从第一存储器接收数据的第一存储器寄存器和与第一存储器通信的直接存储器访问（DMA）模块。 主机设备还包括从第一存储器接收数据的主机控制模块。 主机设备还包括与第一存储器寄存器，主机控制模块和包括第一存储器阵列的第二存储器通信的DMA控制模块。 DMA控制模块将第一存储器阵列的内容与存储器寄存器的内容进行比较，并且基于比较控制从第一存储器到外围控制模块的数据传输。
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公开(公告)号：US20100272162A1
公开(公告)日：2010-10-28
申请号：US12604193
申请日：2009-10-22
申请人： Claire Simeon , Ronak Patel , Mark N. Fullerton
发明人： Claire Simeon , Ronak Patel , Mark N. Fullerton
IPC分类号： H04B1/38
CPC分类号： G06F13/385
摘要： A synchronous serial programmable interface that programmably defines a plurality of frame definitions in which each frame definition provides signal timing for a corresponding frame used in serial data transfer. A sequencer module is used to provide a plurality of instructions, in which each instruction, when executed, obtains a frame definition from the plurality of frame definitions. Then a task scheduler selects a scheduled task from a plurality of tasks that are used in transferring data. The particular task selects one or more instructions from the plurality of instructions and obtains one or more frame definitions specified by the instruction or instructions to establish one or more frames that are used in transferring the data.
摘要翻译： 一种可编程定义多个帧定义的同步串行可编程接口，其中每个帧定义为串行数据传输中使用的相应帧提供信号定时。 定序器模块用于提供多个指令，其中每个指令在执行时从多个帧定义中获得帧定义。 然后，任务调度器从用于传送数据的多个任务中选择调度任务。 特定任务从多个指令中选择一个或多个指令，并且获得由指令或指令指定的一个或多个帧定义，以建立用于传送数据的一个或多个帧。
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公开(公告)号：US20080140878A1
公开(公告)日：2008-06-12
申请号：US11953552
申请日：2007-12-10
申请人： Ofer Bar-Shalom , Mark N. Fullerton , Alon Tsafrir
发明人： Ofer Bar-Shalom , Mark N. Fullerton , Alon Tsafrir
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.
摘要翻译： 主机设备包括外围控制模块，其包括从第一存储器接收数据的第一存储器寄存器和与第一存储器通信的直接存储器访问（DMA）模块。 主机设备还包括从第一存储器接收数据的主机控制模块。 主机设备还包括与第一存储器寄存器，主机控制模块和包括第一存储器阵列的第二存储器通信的DMA控制模块。 DMA控制模块将第一存储器阵列的内容与存储器寄存器的内容进行比较，并且基于比较控制从第一存储器到外围控制模块的数据传输。
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公开(公告)号：US08812889B2
公开(公告)日：2014-08-19
申请号：US12774479
申请日：2010-05-05
CPC分类号： G06F13/1668 , G06F1/3203 , G06F1/3275 , Y02D10/13 , Y02D10/14
摘要： Controlling access to memory includes receiving a plurality of memory access requests and assigning corresponding time values to each. The assigned time values are adjusted based upon a clock pulse and a priority access list is generated. Factors consider include missed access deadlines, closeness to missing access deadlines, and whether a page is open. The highest ranked client is then passed to a sequencer to allow the requested access. Time values may be assigned and adjusted according to client ID or client type (latency or bandwidth). A plurality of power modes of operation are defined wherein operation in a selected power mode of operation is based at least in part on the assigned or adjusted time values. The processing is performed in hardware in parallel (at the same time) by associated logic circuits.
摘要翻译： 控制对存储器的访问包括接收多个存储器访问请求并将相应的时间值分配给每个。 基于时钟脉冲调整分配的时间值，并且生成优先权访问列表。 考虑的因素包括错过访问期限，接近缺少访问截止日期以及页面是否打开。 然后将最高排名的客户端传递给定序器以允许请求的访问。 时间值可以根据客户端ID或客户端类型（延迟或带宽）进行分配和调整。 定义了多个功率工作模式，其中所选择的功率操作模式中的操作至少部分地基于分配或调整的时间值。 处理通过相关的逻辑电路并行（同时）在硬件中执行。
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公开(公告)号：US20130138936A1
公开(公告)日：2013-05-30
申请号：US13752961
申请日：2013-01-29
IPC分类号： G06F9/00
CPC分类号： G06F9/00 , G06F1/06 , G06F1/189 , G06F1/26 , G06F1/3203 , G06F1/3287 , G06F1/3296 , Y02D10/171 , Y02D10/172 , Y02D50/20
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.
摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件根据存储器映射进行操作，存储器映射包括与为多个辐条模块保留的存储器相对应的多个第一保留块，以及对应于至少一个可选辐条模块保留的存储器的至少一个第二保留块。 基于配置数据激活多个第一保留块，并且基于配置数据停用至少一个第二保留块。
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公开(公告)号：US20110264901A1
公开(公告)日：2011-10-27
申请号：US12767201
申请日：2010-04-26
IPC分类号： G06F15/177 , G06F1/04 , G06F1/24 , G06F12/02
CPC分类号： G06F1/3296 , G06F1/266 , G06F1/3237 , G06F1/324 , Y02D10/126 , Y02D10/128 , Y02D10/172
摘要： A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The spoke modules include a plurality of interface circuits each having a hardware address. A memory module stores the hub software and hub data and configuration data. The hub software includes a plurality of driver modules corresponding to the plurality of interface circuits. The processing module executes boot firmware to configure the plurality of driver modules based on the hardware address of each of the plurality of interface circuits.
摘要翻译： 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 辐条模块包括多个具有硬件地址的接口电路。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件包括对应于多个接口电路的多个驱动器模块。 处理模块基于多个接口电路中的每一个的硬件地址执行引导固件以配置多个驱动器模块。
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