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公开(公告)号:US12219857B2
公开(公告)日:2025-02-04
申请号:US17623798
申请日:2020-06-23
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Kazunori Watanabe , Koji Kusunoki , Susumu Kawashima , Taisuke Kamada , Ryo Hatsumi , Daisuke Kubota
IPC: H10K59/65 , G06F3/042 , H10K30/40 , H10K30/82 , H10K39/30 , H10K50/828 , H10K50/86 , H10K59/122 , H10K59/38 , H10K59/40 , G06F3/041 , H10K102/00
Abstract: A display apparatus having a photosensing function is provided. The display apparatus includes a first pixel circuit and a second pixel circuit. The first pixel circuit includes a light-receiving device, a first transistor, and a second transistor. The second pixel circuit includes a light-emitting device. The light-receiving device includes a first pixel electrode, an active layer, and a common electrode. The light-emitting device includes a second pixel electrode, a light-emitting layer, and the common electrode. The active layer is positioned over the first pixel electrode and includes a first organic compound. The light-emitting layer is positioned over the second pixel electrode and includes a second organic compound different from the first organic compound. The common electrode includes a portion overlapping with the first pixel electrode with the active layer therebetween and a portion overlapping with the second pixel electrode with the light-emitting layer therebetween. The first transistor includes low-temperature polysilicon as a semiconductor layer and the second transistor includes a metal oxide as a semiconductor layer.
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公开(公告)号:US11922859B2
公开(公告)日:2024-03-05
申请号:US17048687
申请日:2019-05-08
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Koji Kusunoki , Kazunori Watanabe
CPC classification number: G09G3/32 , G06F3/0412 , G06F3/044 , G06F3/046 , G09G2300/0814 , G09G2310/0202 , G09G2310/0243 , G09G2320/064 , G09G2320/0646 , G09G2354/00
Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a pixel comprising a pixel circuit and a display element, and the display element is electrically connected to the pixel circuit. The pixel circuit is supplied with a selection signal, an image signal, and a pulse width control signal, supplies an output potential, and determines, on the basis of the pulse width control signal, a period during which the output potential is supplied. The pixel circuit includes a first switch and a first transistor. The first switch supplies the image signal on the basis of the selection signal and determines the output potential on the basis of the image signal. The first transistor includes a first and second electrode, and a first gate electrode. The output potential is output from the first electrode, and the first gate electrode is supplied with the image signal.
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公开(公告)号:US11842705B2
公开(公告)日:2023-12-12
申请号:US17844931
申请日:2022-06-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Susumu Kawashima , Koji Kusunoki , Kazunori Watanabe , Naoto Kusumoto
IPC: G09G3/34 , G09G3/36 , G02F1/1368
CPC classification number: G09G3/3648 , G02F1/1368 , G09G3/3696 , G09G2300/0426 , G09G2330/021
Abstract: A display apparatus with low-power consumption is provided. The display apparatus includes an inverter circuit and a pixel having a function of adding data, and the inverter circuit has a function of inverting data supplied from a source driver. The inverter circuit has a function of inverting data supplied from a source driver. The pixel has a function of adding data supplied from the source driver and the inverter circuit. Accordingly, the pixel can generate a voltage several times higher than the output voltage of the source driver and can supply the voltage to a display device. With such a structure, the output voltage of the source driver can be lowered, so that a display apparatus with low power consumption can be achieved.
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公开(公告)号:US11823614B2
公开(公告)日:2023-11-21
申请号:US17052833
申请日:2019-05-09
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Kazunori Watanabe , Kei Takahashi , Koji Kusunoki , Takahiro Fukutome
IPC: G09G3/32 , H01L25/075 , H01L27/12 , H01L29/786 , H01L33/62 , H10K59/90 , H10K71/00 , G09G3/3225
CPC classification number: G09G3/32 , G09G3/3225 , H01L25/0753 , H01L27/1225 , H01L27/1255 , H01L29/7869 , H01L29/78648 , H01L33/62 , H10K59/90 , H10K71/00 , G09G2300/0426 , G09G2300/0809 , G09G2320/0238 , G09G2330/021 , H01L2933/0066
Abstract: A novel display device where a light-emitting element is turned on by a triangle wave is provided. One embodiment of the present invention is a method for driving a display device including a first pixel, a second pixel, a first wiring, a second wiring, and a third wiring. The first wiring is electrically connected to the first pixel and the second pixel. The second wiring and the third wiring are electrically connected to the first pixel and the second pixel, respectively. At a first time, the first pixel reaches the maximum luminance corresponding to first display data and the second pixel reaches the maximum luminance corresponding to second display data. The first pixel and the second pixel are initialized at a second time different from the first time by input of a reset signal to the first wiring to stop light emission.
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公开(公告)号:US11817698B2
公开(公告)日:2023-11-14
申请号:US17256667
申请日:2019-06-25
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Kei Takahashi , Koji Kusunoki , Kouhei Toyotaka , Kazunori Watanabe
IPC: H02J7/00 , G01R31/396 , G01R31/3835 , H01L29/786
CPC classification number: H02J7/007182 , G01R31/3835 , G01R31/396 , H02J7/0048 , H01L29/7869
Abstract: A battery management circuit with a novel structure and a power storage device including the battery management circuit are provided. The power storage device includes a plurality of battery cells connected in series and a battery management circuit. The battery management circuit includes a voltage monitor circuit having a function of acquiring a voltage value between a pair of electrodes of any one of the battery cells. The voltage monitor circuit includes a multiplexer and a buffer circuit for outputting a signal for controlling the multiplexer. The multiplexer and the buffer circuit each include an n-channel transistor. The n-channel transistor is a transistor including an oxide semiconductor in a channel formation region. The multiplexer has a function of retaining an output voltage of the battery cell by setting the transistor in an off state.
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公开(公告)号:US11778878B2
公开(公告)日:2023-10-03
申请号:US17711172
申请日:2022-04-01
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Shunpei Yamazaki , Koji Kusunoki , Kazunori Watanabe , Susumu Kawashima , Kei Takahashi
IPC: G09G3/32 , H10K59/131 , G06N3/04 , G06N3/063 , H01L25/065 , H01L27/15 , H10K59/18
CPC classification number: H10K59/131 , G06N3/04 , G06N3/063 , G09G3/32 , H01L25/0652 , H01L27/156 , H10K59/18 , G09G2300/026
Abstract: A novel display panel that is highly convenient or reliable is provided. A novel display device is provided. The display panel includes a display region, a first terminal region, and a second terminal region, and the first terminal region is provided not to block the display region and includes a region overlapping with the display region. The first terminal region includes a first group of terminals, and the first group of terminals includes a first terminal. The second terminal region includes a second group of terminals, and the second group of terminals includes a second terminal. The display region includes one group of pixels, another group of pixels, a scan line, and a signal line. The one group of pixels includes a pixel and is arranged in a row direction. The another group of pixels includes the pixel and is arranged in a column direction intersecting the row direction. The scan line is electrically connected to the one group of pixels. The signal line is electrically connected to the another group of pixels, and the signal line is electrically connected to the first terminal and the second terminal.
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公开(公告)号:US11735134B2
公开(公告)日:2023-08-22
申请号:US17425766
申请日:2020-01-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Kazunori Watanabe , Koji Kusunoki
IPC: G09G3/36 , G02F1/1362 , G02F1/1368 , G11C19/28
CPC classification number: G09G3/3677 , G02F1/1368 , G02F1/136286 , G09G3/3611 , G11C19/28 , G09G2310/0267 , G09G2310/0286
Abstract: A display apparatus with low power consumption is provided. The display apparatus includes a circuit for boosting a signal voltage output from a gate driver. The signal voltage from the gate driver can be boosted and then supplied to a pixel, which is suitable for driving a display device with a high threshold voltage. Furthermore, by utilizing a boosting function, output of the gate driver can be reduced, and power consumption can also be reduced. By combination with a pixel having a boosting function of image data, a display apparatus with lower power consumption can be achieved.
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公开(公告)号:US11562675B2
公开(公告)日:2023-01-24
申请号:US17269736
申请日:2019-09-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Kouhei Toyotaka , Kazunori Watanabe , Susumu Kawashima , Daisuke Kubota , Tetsuji Ishitani , Akio Yamashita
Abstract: A flip-flop circuit is provided. A driver circuit is provided. The flip-flop circuit includes first to fifth input terminals and first to third output terminals, the first input terminal is supplied with a first trigger signal, the second input terminal is supplied with a second trigger signal, the third input terminal is supplied with a batch selection signal, the fourth input terminal is supplied with a first pulse width modulation signal, and the fifth input terminal is supplied with a second pulse width modulation signal. The first output terminal supplies a first selection signal in response to the first pulse width modulation signal in a period from supply of the first trigger signal to supply of the second trigger signal, the first output terminal supplies the first selection signal in a period during which the batch selection signal is supplied, the second output terminal supplies a second selection signal in response to the second pulse width modulation signal in the period from the supply of the first trigger signal to the supply of the second trigger signal, and the third output terminal supplies a third trigger signal.
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公开(公告)号:US11508307B2
公开(公告)日:2022-11-22
申请号:US17273818
申请日:2019-08-30
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor: Kei Takahashi , Koji Kusunoki , Kouhei Toyotaka , Susumu Kawashima , Kazunori Watanabe
IPC: G09G3/3258 , H01L25/16 , H01L27/32
Abstract: A display device that can correct the threshold voltage of a driving transistor without a correction of image data is provided. A display device including a pixel provided with a driving transistor, a display element, and a memory circuit and a correction data generation circuit is related. One of a source and a drain of the driving transistor is electrically connected to one electrode of the display element, and a gate of the driving transistor is electrically connected to the memory circuit. In a first period, the correction data generation circuit generates correction data that is data for correcting the threshold voltage of the driving transistor. In a second period, first data is written to the memory circuit. In a third period, second data is supplied to the pixel, whereby third data in which the second data is added to the first data is generated. In a fourth period, an image corresponding to the third data is displayed by the display element.
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公开(公告)号:US10957720B2
公开(公告)日:2021-03-23
申请号:US16760495
申请日:2018-10-29
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Kei Takahashi , Susumu Kawashima , Koji Kusunoki , Kazunori Watanabe
Abstract: To provide a display device having a small circuit area and low power consumption. The display device includes a semiconductor device and a D/A converter circuit, and the semiconductor device includes first to third transistors and first and second capacitors. A first terminal of the first transistor is electrically connected to a first terminal of the first capacitor. A first terminal of the second transistor is electrically connected to a gate of the third transistor, a second terminal of the first capacitor, and a first terminal of the second capacitor. A first terminal of the third transistor is electrically connected to a second terminal of the second capacitor. An output terminal of the D/A converter circuit is electrically connected to a second terminal of the first transistor and a second terminal of the second transistor. Supply of a potential to the first terminal of the first capacitor changes (finely adjusts) the potential of the gate of the third transistor to be more precise than a potential that can be output from the D/A converter circuit.
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