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21.发明授权公开(公告)号：US06848025B2
公开(公告)日：2005-01-25
申请号：US10045127
申请日：2001-10-26
CPC分类号： G06F12/123
摘要： A caching device using an N-way replacement mechanism is disclosed. The replacement mechanism comprises at least one replacement order list with N positions, with the first-to-replace position at one end and the last-to-replace position at the opposite end, each position containing a way number, N way comparators, a control unit, a replacement order generator, and receiving a hit signal and, in case of a hit, a hit way number. A system and method in accordance with the present invention provides a programmable replacement mechanism applicable to caching devices, such as instruction and data caches and TLBs (translation lookaside buffers) in processors or texture map caches in graphics systems, that use set associative or fully associative organization. A replacement order list is maintained that specifies the order of which the elements in a set are to be selected for replacement.
摘要翻译： 公开了一种使用N路置换机构的缓存装置。 替换机构包括具有N个位置的至少一个替换订单列表，一端的第一替换位置和相对端的最后替换位置，每个位置包含路数，N路比较器， 控制单元，替换订单发生器，以及接收命中信号，并且在命中的情况下，命中方式号。 根据本发明的系统和方法提供了一种可应用于缓存设备的可编程替换机制，诸如图形系统中的处理器或纹理映射高速缓存中的指令和数据高速缓存以及TLB（转换后备缓冲器），其使用集合关联或完全关联 组织。 维护替换订单列表，其指定要选择要替换的集合中的元素的顺序。
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22.发明授权
公开(公告)号：US5805877A
公开(公告)日：1998-09-08
申请号：US718027
申请日：1996-09-23
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A data processor (10) has a BTAC (48) storing a number of recently encountered fetch address-target address pairs. A branch unit (20) generates a fetch address that depends upon a condition precedent and a received branch instruction. After executing each branch instruction, the branch unit predicts whether the condition precedent will be met the next time it encounters the same branch instruction. If the predicted value of the condition precedent would cause the branch to be taken, then the branch unit adds the fetch address-target address pair corresponding to the branch instruction to the BTAC. If the predicted value of the condition precedent would cause the branch to be not taken, then the branch unit deletes the fetch address-target address pair corresponding to the branch instruction from the BTAC.
摘要翻译： 数据处理器（10）具有存储多个最近遇到的提取地址目标地址对的BTAC（48）。 分支单元（20）生成取决于先决条件和接收到的分支指令的取出地址。 在执行每个分支指令之后，分支单元预测下一次遇到相同的分支指令时是否满足条件先例。 如果先决条件的预测值将导致分支，则分支单元将对应于分支指令的获取地址 - 目标地址对添加到BTAC。 如果先决条件的预测值不会导致分支，则分支单元从BTAC删除与分支指令相对应的获取地址 - 目标地址对。
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23.发明授权Small and power-efficient cache that can provide data for background DMA devices while the processor is in a low-power state 有权小而高功效的缓存，可在处理器处于低功耗状态时为背景DMA设备提供数据公开(公告)号：US07958312B2
公开(公告)日：2011-06-07
申请号：US11559069
申请日：2006-11-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F1/3225 , G06F12/0802 , G06F12/0808 , G06F12/0864 , G06F12/0888 , G06F2212/1028 , G06F2212/6046 , Y02D10/13
摘要： Small and power-efficient buffer/mini-cache sources and sinks selected DMA accesses directed to a memory space included in a coherency domain of a microprocessor when cached data in the microprocessor is inaccessible due to any or all of the microprocessor being in a low-power state not supporting snooping. Satisfying the selected DMA accesses via the buffer/mini-cache enables reduced power consumption by allowing the microprocessor (or portion thereof) to remain in the low-power state. The buffer/mini-cache may be operated (temporarily) incoherently with respect to the cached data in the microprocessor and flushed before deactivation to synchronize with the cached data when the microprocessor (or portion thereof) transitions to a high-power state that enables snooping. Alternatively the buffer/mini-cache may be operated in a manner (incrementally) coherent with the cached data. The microprocessor implements one or more processors having associated cache systems (such as various arrangements of first-, second-, and higher-level caches).
摘要翻译： 当微处理器中的缓存数据由于任何或所有微处理器处于低电平状态时，微处理器中的高速缓存数据不可访问时，小型和功率高效的缓冲器/微型高速缓冲存储器源和接收器被选择指向微处理器的相干域中的存储器空间， 电源状态不支持窥探。 通过缓冲器/微型缓存来满足所选择的DMA访问通过允许微处理器（或其一部分）保持在低功率状态来降低功耗。 缓冲器/微型高速缓存可以相对于微处理器中的高速缓存数据非相干地操作（暂时地），并且在微处理器（或其部分）转换到启用窥探的高功率状态之前，在去激活之前刷新以与缓存的数据同步 。 或者，缓冲器/微型缓存可以以与缓存的数据相一致的方式（递增地）操作。 微处理器实现具有相关联的高速缓存系统（例如第一，第二和更高级别高速缓存的各种布置）的一个或多个处理器。
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公开(公告)号：US07904659B2
公开(公告)日：2011-03-08
申请号：US11559133
申请日：2006-11-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0875 , G06F12/0888 , G06F13/1694 , G06F2212/1028 , G06F2212/2515 , Y02D10/13 , Y02D10/14
摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein. In one usage scenario, data retained in the buffer/mini-cache is graphics refresh data maintained in a compressed format.
摘要翻译： 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下，当CPU开始在低功耗状态下运行时，与缓存/微型缓存进行匹配的非缓存访问（例如由DMA设备产生的）与指定的物理地址范围匹配，而不是由存储器控制器 和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。 在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。 在一种使用场景中，保留在缓冲/微型缓存中的数据是以压缩格式维护的图形刷新数据。
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公开(公告)号：US07899990B2
公开(公告)日：2011-03-01
申请号：US11559192
申请日：2006-11-13
IPC分类号： G06F13/00
CPC分类号： G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F12/0802 , G06F12/0888 , G06F2212/2515 , Y02D10/13 , Y02D10/14
摘要： Power conservation via DRAM access reduction is provided by a buffer/mini-cache selectively operable in a normal mode and a buffer mode. In the buffer mode, entered when CPUs begin operating in low-power states, non-cacheable accesses (such as generated by a DMA device) matching specified physical address ranges, or having specific characteristics of the accesses themselves, are processed by the buffer/mini-cache, instead of by a memory controller and DRAM. The buffer/mini-cache processing includes allocating lines when references miss, and returning cached data from the buffer/mini-cache when references hit. Lines are replaced in the buffer/mini-cache according to one of a plurality of replacement policies, including ceasing replacement when there are no available free lines. In the normal mode, entered when CPUs begin operating in high-power states, the buffer/mini-cache operates akin to a conventional cache and non-cacheable accesses are not processed therein.
摘要翻译： 通过DRAM访问减少的功率节省由在正常模式和缓冲模式下选择性地操作的缓冲器/微型缓存器提供。 在缓冲模式下，当CPU开始在低功率状态下运行时，与缓存/存储器相关的特定物理地址范围匹配或具有访问本身的特定特性的非缓存访问（例如由DMA设备生成） 微型缓存，而不是由存储器控制器和DRAM。 缓冲/微型缓存处理包括在引用未命中时分配线路，以及当引用命中时从缓冲器/微型缓存器返回缓存数据。 根据多个替换策略中的一个替换策略，在缓冲器/微型缓存中替换行，包括当没有可用的空行时停止替换。 在正常模式下，当CPU开始在高功率状态下运行时，缓冲器/微型缓存类似于常规高速缓存，并且不能处理非缓存访问。
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26.发明授权公开(公告)号：US06957323B2
公开(公告)日：2005-10-18
申请号：US10004338
申请日：2001-11-14
申请人： Seungyoon Peter Song
发明人： Seungyoon Peter Song
CPC分类号： G06F9/30167 , G06F9/3009 , G06F9/3836 , G06F9/384 , G06F9/3851
摘要： This disclosure describes an operand file, a device that combines the functions of a register file, a reservation station, and a rename buffer into single storage element. The advantage of this mechanism is that it eliminates copying results and operands between the register file, reservation station, and rename buffer, thereby greatly simplifying the design and reducing area and power consumption. Furthermore, it can also be used in multithreaded processors that spawn children threads by copying some or all of the parent thread's registers to each of the children thread's registers.
摘要翻译： 本公开描述了操作数文件，将寄存器文件，保留站和重命名缓冲器的功能组合成单个存储元件的设备。 该机制的优点在于它消除了寄存器文件，保留站和重命名缓冲区之间的复制结果和操作数，从而大大简化了设计并减少了面积和功耗。 此外，它还可以用于通过将部分或全部父线程的寄存器复制到每个子线程的寄存器来生成子线程的多线程处理器中。
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27.发明授权Method and system for reordering instructions after dispatch in a processing system 失效在处理系统中调度后重新排序指令的方法和系统
公开(公告)号：US6041167A
公开(公告)日：2000-03-21
申请号：US508121
申请日：1995-07-27
申请人： Seungyoon Peter Song
发明人： Seungyoon Peter Song
CPC分类号： G06F9/3885 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： A processing system and method of operation are provided. A particular instruction is dispatched to execution circuitry for execution. After dispatching the particular instruction, an execution serialized instruction is dispatched to the execution circuitry prior to finishing execution of the particular instruction.
摘要翻译： 提供了一种处理系统和操作方法。 特定指令被发送到执行电路执行。 在分派特定指令之后，在执行特定指令之前将执行序列化指令分派到执行电路。
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28.发明授权Predictive translation of a data address utilizing sets of associative entries stored consecutively in a translation lookaside buffer 失效使用在转换后备缓冲器中连续存储的一组关联条目来预测数据地址的翻译
公开(公告)号：US5893930A
公开(公告)日：1999-04-13
申请号：US678940
申请日：1996-07-12
申请人： Seungyoon Peter Song
发明人： Seungyoon Peter Song
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： A method for performing predictive translation of a data address in a computer processing system includes organizing a translation lookaside buffer in a set associative manner having each set associated with multiple entries, wherein the multiple entries store consecutively ordered selections. Further, the method includes selecting a set of entries in the translation lookaside buffer in response to a base operand for the predictive translation. The method also includes comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed. The method further includes the step of adding the base operand with an offset operand to produce the effective address. A system in accordance with the present invention includes effective address generation logic, including a base operand register to hold a base operand, and a translation lookaside buffer, translation lookaside buffer. The translation lookaside buffer includes a multiple number of entries organized in a set associative manner to map a desired number of consecutive pages into a single set, and coupled to the effective address generation logic to utilize selected bits of the base operand for selection of a set of entries and for comparing each entry in the selected set with an input address for determining whether or not the predictive translation failed.
摘要翻译： 一种用于在计算机处理系统中执行数据地址的预测转换的方法包括以具有与多个条目相关联的每个集合的集合关联方式组织翻译后备缓冲器，其中所述多个条目存储连续排序的选择。 此外，该方法包括响应于用于预测性翻译的基本操作数，在翻译后备缓冲器中选择一组条目。 该方法还包括将所选集合中的每个条目与用于确定预测性翻译是否失败的输入地址进行比较。 该方法还包括将基本操作数与偏移操作数相加以产生有效地址的步骤。 根据本发明的系统包括有效地址生成逻辑，包括用于保存基本操作数的基本操作数寄存器和翻译后备缓冲器，翻译后备缓冲器。 翻译后备缓冲器包括以组合关联方式组织的多个条目，以将期望数量的连续页映射到单个集合中，并且耦合到有效地址生成逻辑，以利用用于选择集合的基本操作数的所选位 并且用于将所选集合中的每个条目与用于确定预测性翻译是否失败的输入地址进行比较。
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29.发明授权Data processor with an execution unit for performing load instructions and method of operation 失效具有用于执行加载指令和操作方法的执行单元的数据处理器
公开(公告)号：US5664215A
公开(公告)日：1997-09-02
申请号：US622159
申请日：1996-03-27
申请人： David P. Burgess , Marvin Denman , Milton M. Hood, Jr. , Mark A. Kearney , Lavanya Kling , Graham R. Murphy , Seungyoon Peter Song
发明人： David P. Burgess , Marvin Denman , Milton M. Hood, Jr. , Mark A. Kearney , Lavanya Kling , Graham R. Murphy , Seungyoon Peter Song
CPC分类号： G06F9/30043 , G06F9/3017 , G06F9/3816 , G06F9/3824 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857
摘要： The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.
摘要翻译： 所公开的数据处理器（10）作为一系列简单的加载或存储指令来调度加载/存储多个并将加载/存储字符串指令加载/存储单元（28）。 定序器单元（18）分配加载/存储单元写入每个简单加载指令的数据的重命名缓冲器（34）的条目。 该策略有助于提前进行数据转发以便后续指令。 相反，如果定序器单元不能提供简单存储指令的操作数，则将重命名缓冲器标签提供给加载/存储单元。
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公开(公告)号：US08281308B1
公开(公告)日：2012-10-02
申请号：US11933199
申请日：2007-10-31
申请人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
发明人： Yu Qing Cheng , John Gregory Favor , Peter N. Glaskowsky , Carlos Puchol , Seungyoon Peter Song
IPC分类号： G06F9/455
CPC分类号： G06F9/455 , G06F9/4825 , Y02D10/24
摘要： A virtual core management system including a first physical core and a second physical core, and a virtual core including a collection of logical states associated with execution of a program. The virtual core management system further includes a first temperature sensor configured to sense a temperature of the first physical core and a second temperature sensor configured to sense a temperature of the second physical core, and a virtual core management component configured to map the virtual core to one of the first physical core and the second physical core based on at least one of the temperature of the first physical core and the temperature of the second physical core.
摘要翻译： 包括第一物理核心和第二物理核心的虚拟核心管理系统以及包括与执行程序相关联的逻辑状态的集合的虚拟核心。 虚拟核心管理系统还包括配置成感测第一物理核心的温度的第一温度传感器和被配置为感测第二物理核心的温度的第二温度传感器，以及配置成将虚拟核心映射到 基于第一物理核心的温度和第二物理核心的温度中的至少一个的第一物理核心和第二物理核心之一。
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