公开(公告)号：US09905590B2

公开(公告)日：2018-02-27

申请号：US14779089

申请日：2015-07-31

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. ,  Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Cong Wang ,  Peng Du ,  Xiaoxiao Wang

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1368

CPC classification number: H01L27/127 ,  G02F1/1368 ,  G02F2202/104 ,  H01L27/1222 ,  H01L27/1248 ,  H01L27/1288 ,  H01L29/78621 ,  H01L29/78675

Abstract: The present invention provides a LTPS array substrate and a manufacturing method thereof. The method comprises: forming a source electrode and a drain electrode on a substrate, forming polysilicon layers of a first region and a second region on the substrate including the source electrode and the drain electrode, and the thickness of the polysilicon layer of the first region is greater than the one of the second region, the polysilicon layer of the first region partially covers the source electrode and the drain electrode; passivating the surface of the polysilicon layer in order to turn the part of the adjacent surface of the polysilicon layer of the second region and the first region into an insulating layer; forming a gate electrode on the insulating layer between the source electrode and the drain electrode. The present invention can simplify the LTPS technical process and reduce the producing costs.

公开(公告)号：US09899425B2

公开(公告)日：2018-02-20

申请号：US14781536

申请日：2015-08-14

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Cong Wang ,  Peng Du

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/66 ,  H01L29/49 ,  H01L29/786 ,  H01L21/225 ,  H01L21/265

CPC classification number: H01L27/124 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: A manufacturing method for an array substrate is provided in the present invention. The method comprises: forming a Poly-Silicon layer on a glass substrate; forming heavily doped regions by performing heavily doping and activation process at both sides of the Poly-Silicon layer; forming a source/a drain of a first metal layer growing on the heavily doped region; forming a gate of both a gate insulator and a second metal layer growing sequentially on the Poly-Silicon layer, wherein, a material of the second metal layer is aluminum. The activation technology process can be improved in the present invention to reduce RC delay in metal wires of product and then further to achieve large sizes for products.

公开(公告)号：US09865619B2

公开(公告)日：2018-01-09

申请号：US14779545

申请日：2015-08-13

Applicant: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

Inventor： Xiaoxiao Wang ,  Peng Du ,  Cong Wang

IPC: H01L27/12 ,  H01L29/786 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/45 ,  H01L29/66 ,  H01L21/22 ,  H01L21/265 ,  G02F1/1368

CPC classification number: H01L27/1222 ,  G02F1/136209 ,  G02F1/1368 ,  G02F2202/104 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/22 ,  H01L21/26513 ,  H01L21/32133 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/786 ,  H01L29/78633 ,  H01L29/78675

Abstract: An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole semiconductor layer on a substrate; simultaneously patterning the semiconductor layer and the light-shading layer; and forming a first insulation layer, a first metal layer, a second insulation layer, a second metal layer, a flat layer, and a first transparent conductive layer on the patterned semiconductor layer.

公开(公告)号：US09805682B2

公开(公告)日：2017-10-31

申请号：US14888698

申请日：2015-09-30

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. ,  Wuhan China Star Optoelectronics Technology Co., Ltd.

Inventor： Cong Wang ,  Peng Du

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G02F1/13 ,  G09G2300/0809 ,  G09G2310/0243 ,  G09G2310/0281 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2310/08

Abstract: Provided are a scanning driving circuit and a liquid crystal display device. The scanning driving circuit comprises multiple cascaded scanning driving units (1). Each scanning driving unit (1) comprises an input module (100) for outputting a low-level signal and a plurality of driving circuits (200). Each driving circuit (200) corresponding drives one scanning line. Each driving circuit (200) comprises: a control module (210), for outputting a control signal according to the received low-level signal; an output module (220), and a pull-down module (230), for being connected or cut off according to the received control signal; scanning lines (G(N−1), G(N), G(N+1)), for outputting a high-level or low-level scanning driving signal to pixel units. When the output module (220) is cut off, the pull-down module (230) is connected, and the scanning lines (G(N−1), G(N), G(N+1)) output the low-level scan driving signals to the pixel units; and when the output module (220) is connected, the pull-down module (230) is cut off, and the scanning lines (G(N−1), G(N), G (N+1)) output high-level scanning driving signals to the pixel units. Accordingly, a circuit of the liquid crystal display device is simplified, and the space is saved, thereby facilitating the narrow-frame design of the liquid crystal display device.

公开(公告)号：US09711540B2

公开(公告)日：2017-07-18

申请号：US14420901

申请日：2015-01-13

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Cong Wang ,  Peng Du

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L27/1255 ,  H01L27/1222 ,  H01L27/1237 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78633 ,  H01L29/78675

Abstract: An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate electrode line and a common electrode line, an insulation layer, a drain electrode and a source electrode, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. The bottom transparent conductive layer, the protection layer, and the top transparent conductive layer are sequentially stacked on the planarization layer. The patternized poly-silicon layer includes a first portion and a second portion. The drain electrode includes an extension section extending therefrom and opposite to the second portion.

公开(公告)号：US09530800B2

公开(公告)日：2016-12-27

申请号：US14435468

申请日：2015-01-21

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Cong Wang ,  Peng Du ,  Lixuan Chen

IPC: H01L27/14 ,  H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/66757 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/78675

Abstract: The invention provides an array substrate, a display panel and a method for preparing an array substrate. The array substrate includes multiple low temperature poly-silicon (LTPS) thin film transistors arranged in an array. Each LTPS thin film transistor includes: a substrate; a LTPS layer, a source, a drain and a first conductive layer disposed on a same surface of the substrate, the source and the drain respectively being arranged at two sides of the LTPS layer and electrically connected with the LTPS layer, the drain being electrically connected with the first conductive layer; an insulating layer disposed on the LTPS layer, the source, the drain and the first conductive layer; a gate disposed on the insulating layer and corresponding to the LTPS layer; a passivation layer disposed on the gate; and a second conductive layer disposed on the passivation layer and corresponding to the first conductive layer.

Abstract translation: 本发明提供一种阵列基板，显示面板及其制备阵列基板的方法。 阵列基板包括排列成阵列的多个低温多晶硅（LTPS）薄膜晶体管。 每个LTPS薄膜晶体管包括：基板; 设置在所述衬底的相同表面上的LTPS层，源极，漏极和第一导电层，所述源极和漏极分别布置在所述LTPS层的两侧并与所述LTPS层电连接，所述漏极电 与第一导电层相连; 设置在LTPS层，源极，漏极和第一导电层上的绝缘层; 设置在绝缘层上并对应于LTPS层的栅极; 设置在栅极上的钝化层; 以及设置在所述钝化层上并对应于所述第一导电层的第二导电层。

公开(公告)号：US09520414B2

公开(公告)日：2016-12-13

申请号：US14370774

申请日：2014-06-18

Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.

Inventor： Cong Wang ,  Ming-Hung Shih ,  Peng Du

IPC: H01L27/12 ,  H01L27/32 ,  G02F1/1362 ,  H01L21/768

CPC classification number: H01L27/124 ,  G02F1/1362 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/3258 ,  H01L27/3262 ,  H01L27/3276

Abstract: The present invention proposes a TFT array substrate includes: a substrate; scan lines on the substrate; data lines intercrossing with the scan lines; a first insulating layer between the scan lines and the data lines; a second insulating layer on the first insulating layer and covering the data lines; a common electrode layer on the second insulating layer, comprising first holes located above the data lines. The first holes uncover the second insulating layer. The present invention decreases parasitic capacitance between the common electrode layer and data lines and between the common electrode layer and scan lines by decreasing overlaping sections between a common electrode layer and the data lines and between the common electrode layer and the scan lines. Therefore load of the data lines and the scan lines decreases, charge efficiency of the pixels increases, and display effect of an LCD panel is therefore improved.

Abstract translation: 本发明提出一种TFT阵列基板，包括：基板; 在基板上扫描线; 数据线与扫描线交叉; 扫描线和数据线之间的第一绝缘层; 在所述第一绝缘层上的第二绝缘层并覆盖所述数据线; 在第二绝缘层上的公共电极层，包括位于数据线之上的第一孔。 第一孔露出第二绝缘层。 本发明通过减小公共电极层与数据线之间以及公共电极层与扫描线之间的重叠部分，减小公共电极层与数据线之间以及公共电极层与扫描线之间的寄生电容。 因此，数据线和扫描线的负载减小，像素的充电效率增加，因此改善了LCD面板的显示效果。